Patents by Inventor Chenyang ZHANG

Chenyang ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138630
    Abstract: The disclosure includes systems and methods for performing gaze-daze-based interaction in virtual reality and mixed reality (XR) environments. An example system includes at least one head-mountable display (HMD) with at least one eye-tracking sensor, and an XR environment with at least one virtual window with a respective level of visual transparency that is responsive to the characteristic gaze depth calculated by the system. The characteristic gaze depth is calculated based on the eye tracking data, and may utilize a noise-reduction model. An example method of creating an XR training environment for users is also disclosed.
    Type: Application
    Filed: October 28, 2024
    Publication date: May 1, 2025
    Inventors: Elaheh Soltanaghaei Koupaei, Eric Gene Shaffer, Chenyang Zhang, Tiansu Chen
  • Patent number: 12278243
    Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a plurality of chips arranged on the base substrate each including a chip main body and a plurality of terminals arranged thereon; a plurality of fixed connection portions arranged on the base substrate, and adjacent to the plurality of chips; a terminal expansion layer arranged on the base substrate; and a plurality of expansion wires in the terminal expansion layer and configured to electrically connect the chips, wherein an expansion wire configured to electrically connect two chips includes at least a first wire segment and a second wire segment, and the first wire segment is configured to electrically connect a terminal of a chip and a fixed connection portion adjacent to the chip, and the second wire segment is configured to connect two fixed connection portions between the two chips.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 15, 2025
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chenyang Zhang, Fuqiang Li, Xue Dong, Meili Wang, Xuan Liang, Fei Wang, Mingxing Wang, Zhanfeng Cao, Yanling Han, Xinxin Zhao
  • Publication number: 20250119120
    Abstract: A multi-inductor common-ground on-chip millimeter wave single-pole double-throw radio frequency switch is provided. The radio frequency switch includes a first radio frequency port, a second radio frequency port, a third radio frequency port, a first switch arm and a second switch arm. Access points of output matching circuits in the two switch arms are respectively connected with a first compensation inductor and a second compensation inductor. The first compensation inductor, the second compensation inductor, and a first coupling inductor connected with the first radio frequency port are multiplexed to be grounded to a second coupling inductor.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Guangxu SHEN, Haitao MA, Chenyang ZHANG, Ye HAN
  • Publication number: 20250093722
    Abstract: An array substrate, a method for manufacturing an array substrate, a liquid crystal cell and a display apparatus are provided. The array substrate includes: a first base substrate; thin film transistors; a first planarization layer; a common electrode on a side of the first planarization layer away from the thin film transistors; a first dielectric layer on a side of the common electrode away from the first planarization layer; first pixel electrodes on a side of the first dielectric layer away from the common electrode; the first pixel electrodes are electrically connected to the thin film transistors in a one-to-one correspondence through first vias extending through the first dielectric layer and the first planarization layer; a surface of each first pixel electrode away from the first base substrate is provided with a first groove at least corresponding to a corresponding first via.
    Type: Application
    Filed: July 26, 2022
    Publication date: March 20, 2025
    Inventors: Yunping DI, Chenyang ZHANG, Lizhong WANG, Yichi ZHANG, Haoliang ZHENG, Zhen ZHANG
  • Publication number: 20250081610
    Abstract: Disclosed are a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a plurality of first circuit regions and a plurality of second circuit regions alternately disposed along a second direction, a first circuit region includes a plurality of repeat units (RU) and a plurality of blank units (KB) alternately disposed along a first direction, a repeat unit (RU) includes a plurality of circuit units (Q), a circuit unit (Q) includes a pixel drive circuit and a data signal line (DataI) connected with the pixel drive circuit, a second circuit region includes at least one gate unit (G), the gate unit includes at least one gate drive circuit, and an orthographic projection of the gate drive circuit on a plane of the display substrate is not overlapped with an orthographic projection of the data signal line (DataI) on the plane of the display substrate.
    Type: Application
    Filed: December 22, 2022
    Publication date: March 6, 2025
    Inventors: Li XIAO, Yan QU, Haoliang ZHENG, Jiao ZHAO, Yuzhen GUO, Xiaorong CUI, Chenyang ZHANG, Minghua XUAN
  • Publication number: 20250081609
    Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. The display substrate includes a plurality of circuit units (Q), the plurality of circuit units (Q) includes at least a first circuit unit (Q1), a second circuit unit (Q2) and a third circuit unit (Q3), wherein the first circuit unit (Q1) includes at least a first drive transistor (DTFT1), the second circuit unit (Q2) includes at least a second drive transistor (DTFT2), the third circuit unit (Q3) includes at least a third drive transistor (DTFT3), the channel width of the first drive transistor (DTFT1) is larger than that of the second drive transistor (DTFT2) or the third drive transistor (DTFT3), and the channel length of the first drive transistor (DTFT1) is the same as that of the second drive transistor (DTFT2) or the third drive transistor (DTFT3).
    Type: Application
    Filed: December 22, 2022
    Publication date: March 6, 2025
    Inventors: Li XIAO, Haoliang ZHENG, Minghua XUAN, Jiao ZHAO, Yuzhen GUO, Xiaorong CUI, Chenyang ZHANG
  • Publication number: 20250076725
    Abstract: A simulation method is provided, including: obtaining a model parameter information, including a total charge quantity and respective charge volume densities of various charged particles, and an external electric field force; calculating a built-in electric field intensity by using the model parameter information and a pre-constructed model, where an input of the model includes the total charge quantity and the respective charge volume densities of the various charged particles; calculating, based on the built-in electric field intensity, a built-in electric field force acting on each charged particle; simulating a motion of each charged particle according to the external electric field force and the built-in electric field force acting on each charged particle; and determining a display grayscale under the external electric field force to obtain a simulation relationship between display grayscale and external electric field force, in response to the motion of each charged particle stopping.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Xiaorong Cui, Yuzhen Guo, Haoliang Zheng, Li Xiao, Chenyang Zhang, Minghua Xuan, Lipeng Gao, Jiao Zhao
  • Patent number: 12235557
    Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 25, 2025
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Zhang, Fuqiang Li, Zhenyu Zhang, Yunping Di, Lizhong Wang, Zheng Fang, Jiahui Han, Yawei Wang, Chenyang Zhang, Chengfu Xu, Ce Ning, Pengxia Liang, Feihu Zhou, Xianqin Meng, Weiting Peng, Qiuli Wang, Binbin Tong, Rui Huang, Tianmin Zhou, Wei Yang
  • Patent number: 12221366
    Abstract: A method for recycling a copper-containing wastewater from a micro-etching is provided, including: modifying a FeS material with a monomer including both carboxyl and sulfhydryl, a crosslinking agent, and a stabilizing and dispersing agent to obtain a FeS-based pH-responsive material CMC-FeS@HS #SiO2 #COOH, adding the FeS-based pH-responsive material to weakly-acidic copper-containing wastewater from the micro-etching to allow a reaction, and conducting processes such as sulfide precipitation, exchange, adsorption complexation, and flocculation precipitation to finally obtain a precipitate with CuS as a main component. This method makes full use of the pH responsiveness and abundant surface active sites of the FeS-based pH-responsive material, and can control a recovery rate of copper ions in the wastewater at 99.8% or more merely by adjusting a pH value of the copper-containing wastewater from the micro-etching.
    Type: Grant
    Filed: August 14, 2024
    Date of Patent: February 11, 2025
    Assignee: CENTRAL SOUTH UNIVERSITY
    Inventors: Chenyang Zhang, Mingjun Han, Wei Sun, Jie Li, Wenjihao Hu, Heng Yu, Rong Wang, Siyuan Liu, Xiangsong Meng, Pan Chen
  • Patent number: 12194495
    Abstract: The present disclosure provides an ultrasonic sensor, a method for driving the same, and a method for manufacturing the same. The ultrasonic sensor includes a back plate, a sounding structure on the back plate and a backing layer on a side of the sounding structure distal to the back plate; the sounding structure includes a plurality of emitting electrodes, an opposite electrode, a piezoelectric layer and a plurality of signal leads, and the plurality of emitting electrodes and the opposite electrode are respectively arranged on two sides of the piezoelectric layer; and the plurality of emitting electrodes are arranged in an array, and each of the emitting electrodes is individually coupled to one of the signal leads. The ultrasonic sensor may achieve an independent control for each patterned electrode such that the ultrasonic sensor may be used as a point sound source.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 14, 2025
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuzhen Guo, Yingming Liu, Haisheng Wang, Xiufeng Li, Lijun Zhao, Peixiao Li, Yaqian Ji, Chenyang Zhang
  • Publication number: 20250014503
    Abstract: A pixel circuit, a pixel driving method and a display device are provided. The pixel circuit includes a driving circuit, a light emitting element and a light emitting gating control circuit; the driving circuit is electrically connected to a first electrode of the light emitting element, and is configured to drive the light emitting element; the light emitting gating control circuit is configured to form a current path between the second electrode of the light emitting element and the first voltage terminal under the control of the first control signal provided by the first control terminal according to the first light emitting control voltage provided by the first light emitting control voltage terminal and the light emitting data voltage provided by the light emitting data voltage terminal, to control the driving circuit to control the light emitting element to emit light.
    Type: Application
    Filed: September 1, 2022
    Publication date: January 9, 2025
    Inventors: Jiao ZHAO, Yuzhen GUO, Haoliang ZHENG, Li XIAO, Chenyang ZHANG, Xiaorong CUI, Minghua XUAN, Wanzhi CHEN, Yan QU
  • Publication number: 20240395212
    Abstract: A display substrate includes a plurality of pixel circuits arranged in an array and a plurality of light emitting devices provided on a substrate, and at least one pixel circuit is connected to a corresponding light emitting device through a conductive structure. At least some of the pixel circuits in at least one column include a first pixel circuit and a second pixel circuit arranged on a side of the first pixel circuit away from the substrate, orthographic projections of the second pixel circuit and the first pixel circuit on the substrate partially overlap to form an overlapping portion defining a first pattern, and an orthographic projection of a conductive structure of the first pixel circuit on the substrate, the first pattern, and an orthographic projection of a conductive structure of the second pixel circuit on the substrate are sequentially arranged in a first direction.
    Type: Application
    Filed: October 29, 2021
    Publication date: November 28, 2024
    Inventors: Chenyang Zhang, Zhenyu Zhang, Hongrun Wang, Haixu Li, Fuqiang Li
  • Publication number: 20240257772
    Abstract: A display panel, a method for driving a display panel, and a display apparatus are provided. The display panel includes a first base substrate and a plurality of pixels on one side of the first base substrate. Each pixel includes: a plurality of pixel sub-electrodes independent from each other and configured to form an electric field with an included angle greater than 0 with respect to a direction perpendicular to the first base substrate under control of incompletely same driving signals; a common electrode on a side of the pixel electrode away from the first base substrate; and an electrophoretic liquid layer between the pixel electrode and the common electrode, including a plurality of charged particles therein.
    Type: Application
    Filed: September 5, 2022
    Publication date: August 1, 2024
    Inventors: Yuzhen GUO, Haoliang ZHENG, Minghua XUAN, Hebin ZHAO, Meirong LU, Chenyang ZHANG, Li XIAO, Xiaorong CUI, Jiao ZHAO, Shulei LI, Weixing LIU, Jintao PENG, Chunfang ZHANG, Xinxing WANG, Zhiqiang XU, Wanpeng TENG, Kai GUO
  • Publication number: 20240223936
    Abstract: A display panel and a fabricating method are provided. Display panel includes a display assembly and sound generation assemblies. The display assembly comprises a display assembly substrate and a plurality of pixel components. Each sound generation assembly comprises a vibrating membrane and an exciter. The exciter comprises a motion part in contact with the vibrating membrane and a drive part driving the motion part to vibrate, and the motion part vibrates to drive the vibrating membrane to vibrate. The display assembly substrate and the vibrating membrane are the same structure. The pixel components are disposed on a side of the vibrating membrane facing away from the exciter. A projection of the each sound generation assembly on the display assembly substrate covers projections of at least two pixel components on the display assembly substrate.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Yaqian JI, Xue DONG, Wei SUN, Yingming LIU, Wenchao HAN, Xiaoliang DING, Xiufeng LI, Yanling HAN, Lianghao ZHANG, Chenyang ZHANG, Yuzhen GUO, Peixiao LI, Yue GOU
  • Patent number: 12021173
    Abstract: A light-emitting diode (LED) chip includes a plurality of epitaxial structures, at least one first electrode, and a plurality of second electrodes. Any two adjacent epitaxial structures of the plurality of epitaxial structures have a gap therebetween. Each epitaxial structure includes a first semiconductor pattern, a light-emitting pattern and a second semiconductor pattern stacked in sequence. First semiconductor patterns in at least two of the plurality of epitaxial structures are connected to each other to form a first semiconductor layer. A first electrode is electrically connected to the first semiconductor layer. Each second electrode is electrically connected to the second semiconductor pattern in at least one of the plurality of epitaxial structures.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: June 25, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mingxing Wang, Binbin Tong, Lizhen Zhang, Chenyang Zhang, Zhen Zhang, Xiawei Yun, Guangcai Yuan, Xue Dong, Muxin Di, Zhiwei Liang, Ke Wang, Zhanfeng Cao
  • Publication number: 20240204002
    Abstract: Embodiments of the present disclosure provide an array substrate and method for manufacturing same, a display panel, and a display device, and relate to the field of display technologies. The array substrate includes a color filter layer, such that a distance between a light source on a side, distal from the color filter layer, of the base substrate and the color filter layer is less. Thus, light from regions of the color resist blocks is avoided being emitted from adjacent color resist blocks, and a cross color of the display panel is further avoided, such that the display effect of the display panel is great. In addition, the color resist block is at least partially overlapped with a second portion of a metal oxide pattern in an oxide thin film transistor, such that an overall footprint of the oxide thin film transistor and the color filter layer can be reduced, so as to acquire the display panel of high PPI.
    Type: Application
    Filed: October 28, 2021
    Publication date: June 20, 2024
    Inventors: Zhen ZHANG, Fuqiang LI, Zhenyu ZHANG, Lizhong WANG, Yunping DI, Ce NING, Zheng FANG, Chenyang ZHANG, Yawei WANG, Wei WANG, Hongrun WANG, Binbin TONG, Nianqi YAO, Jiahui HAN, Chengfu XU, Pengxia LIANG
  • Publication number: 20240203343
    Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display region is provided with a pixel circuit and a light emitting unit; each pixel circuit is connected with K light emitting devices emitting light of a same color; each pixel circuit includes a current control sub-circuit and a light emitting selection sub-circuit; the current control sub-circuit is configured to provide a drive current to a first node under control of a reset signal terminal, an initial signal terminal, a scan signal terminal, a data signal terminal, a light emitting control terminal, and a first power supply terminal; the light emitting selection sub-circuit is configured to sequentially provide a signal of the first node to the K light emitting devices emitting light of the same color under control of K light emitting selection signal terminals.
    Type: Application
    Filed: September 23, 2021
    Publication date: June 20, 2024
    Inventors: Yuzhen GUO, Zhenyu ZHANG, Lubin SHI, Zhen ZHANG, Chenyang ZHANG, Fuqiang LI
  • Patent number: 12016249
    Abstract: A piezoelectric sensor and a manufacturing method thereof, a method for recognizing a fingerprint, and an electronic device are disclosed. The piezoelectric sensor includes a first electrode layer and a second electrode layer which are opposite to each other and a piezoelectric layer. The piezoelectric layer is between the first electrode layer and the second electrode layer and includes a plurality of piezoelectric units arranged at intervals and an insulation layer between adjacent piezoelectric units of the plurality of piezoelectric units. The first electrode layer includes a plurality of sub-electrodes corresponding to the plurality of piezoelectric units, or the second electrode layer includes a plurality of sub-electrodes corresponding to the plurality of piezoelectric units; or both the first electrode layer and the second electrode layer include a plurality of sub-electrodes corresponding to the plurality of piezoelectric units.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 18, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiufeng Li, Yingming Liu, Yuzhen Guo, Chenyang Zhang
  • Patent number: 11991496
    Abstract: A display panel, a fabricating method and a control method thereof and a display device are provided. Display panel includes a display assembly and sound generation assemblies. Display assembly includes a display assembly substrate and pixel components disposed on a side of display assembly substrate. Each sound generation assembly includes a vibrating membrane, an exciter, and a support structure. Support structure is disposed on a side of vibrating membrane and has a cavity. Exciter includes a motion part in contact with vibrating membrane and a drive part disposed in cavity. Drive part drives motion part to vibrate, and motion part vibrates to drive vibrating membrane to vibrate. Display assembly substrate and vibrating membrane are the same structure, and pixel components are disposed on a side of vibrating membrane facing away from support structure. Display device includes the display panel above.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: May 21, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yaqian Ji, Xue Dong, Wei Sun, Yingming Liu, Wenchao Han, Xiaoliang Ding, Xiufeng Li, Yanling Han, Lianghao Zhang, Chenyang Zhang, Yuzhen Guo, Peixiao Li, Yue Gou
  • Publication number: 20240162247
    Abstract: Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.
    Type: Application
    Filed: June 29, 2021
    Publication date: May 16, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Fuqiang Li, Zhen Zhang, Zhenyu Zhang, Lizhong Wang, Ce Ning, Yunping Di, Zheng Fang, Jiahui Han, Chenyang Zhang, Yawei Wang, Chengfu Xu