Abstract: Embodiments of the present disclosure relate to a method and apparatus for mapping processing. The method comprises acquiring a first table and a second table, and determining a first header of the first table and a second header of the second table based on received attribute setting information. The method further comprises acquiring a group of column names from the first header and the second header, wherein the group of column names includes a first column name in the first table and a second column name in the second table. The method also comprises mapping the group of column names to a mapped column name; merging the first table and the second table based on the mapped column name and outputting a merged table.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for mapping processing. The method comprises acquiring a first table and a second table, and determining a first header of the first table and a second header of the second table based on received attribute setting information. The method further comprises acquiring a group of column names from the first header and the second header, wherein the group of column names includes a first column name in the first table and a second column name in the second table. The method also comprises mapping the group of column names to a mapped column name; merging the first table and the second table based on the mapped column name and outputting a merged table.

Abstract: A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption.

Abstract: A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption.