Patents by Inventor Chen-Yu Wu
Chen-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12395156Abstract: A terminal correction circuit includes a first terminal replica model, a terminal voltage offset correction circuit, a second terminal replica model and a terminal resistance offset correction circuit. The first terminal replica model sets a resistance ratio of first and second adjustable resistors according to a voltage correction code, thereby adjusting a terminal voltage. The terminal voltage offset correction circuit compares the terminal voltage and a third power supply voltage and provides the voltage correction code according to the comparison result. The second terminal replica model sets a resistance ratio of third and fourth adjustable resistors according to the voltage correction code and reduces an equivalent resistance value between a half-voltage terminal and a ground voltage according to a resistance correction code.Type: GrantFiled: March 7, 2024Date of Patent: August 19, 2025Assignee: Winbond Electronics Corp.Inventors: Chen-Yu Wu, Tzu-Chao Wu
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Publication number: 20250253830Abstract: A terminal correction circuit includes a first terminal replica model, a terminal voltage offset correction circuit, a second terminal replica model and a terminal resistance offset correction circuit. The first terminal replica model sets a resistance ratio of first and second adjustable resistors according to a voltage correction code, thereby adjusting a terminal voltage. The terminal voltage offset correction circuit compares the terminal voltage and a third power supply voltage and provides the voltage correction code according to the comparison result. The second terminal replica model sets a resistance ratio of third and fourth adjustable resistors according to the voltage correction code and reduces an equivalent resistance value between a half-voltage terminal and a ground voltage according to a resistance correction code.Type: ApplicationFiled: March 7, 2024Publication date: August 7, 2025Applicant: Winbond Electronics Corp.Inventors: Chen-Yu Wu, Tzu-Chao Wu
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Patent number: 12381170Abstract: Achieving homogeneous and heterogeneous integration for 2.5D and 3D integrated circuit, chip-to-wafer, chip-to-substrate, or wafer-to-wafer bonding is an essential technology. The landing wafer or substrate is bonded with a carrier by using a temporary bonding material before thinning the landing wafer to the desired thickness. Upon completion of redistribution layer formation, Cu pad formation, or other backside processing, dies or wafers with through-silicon vias are stacked onto the landing substrate before molding and singulation. As the landing wafer usually has interconnection metals in the bond line, and those interconnection metals are typically made from lead-free solder alloys, deformation of those solder alloys during thermocompression bonding becomes an issue for manufacturers. To address this issue, a polymeric material with desired strengths is coated on the device wafer to form a conformal protective layer on top of solder alloys, thus enabling temporary bonding and debonding processes.Type: GrantFiled: February 15, 2022Date of Patent: August 5, 2025Assignee: Brewer Science, Inc.Inventors: Chia-Hsin Lee, Alice Guerrero, Arthur O. Southard, Chen-Yu Wu, Xiao Liu
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Publication number: 20250210005Abstract: A panel driving device includes panel. Panel includes data line, reference electrode line and first pixel. Data line transmits data signal. Reference electrode line transmits reference signal. First pixel generates pixel signal according to data signal and reference signal. During positive frame period, difference between first voltage value of pixel signal and first reference voltage value of reference signal is first driving voltage value. During negative frame period, difference between second voltage value of pixel signal and second reference voltage value of reference signal is second driving voltage value. Absolute value of first driving voltage value is about the same as absolute value of second driving voltage value. During charging period which is between negative and positive frame periods, pixel signal has a third voltage value, which is greater than second voltage value, and third voltage value is less than or equal to first voltage value.Type: ApplicationFiled: October 30, 2024Publication date: June 26, 2025Inventors: Chu-Kuan YU, Che-Min Lin, Chun-Ru Huang, Fang-Ming Tsao, Kai-Teng Chiang, Chen-Yu Wu
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Publication number: 20250199365Abstract: A display panel including a first substrate, a second substrate, a first protruding structure, a second protruding structure, and a light-shielding pattern layer is provided. The first protruding structure is disposed on the first substrate. The second protruding structure is disposed on the second substrate, and is adapted to abut against the first protruding structure. A width of the first protruding structure along a first direction is less than a width of the second protruding structure along the first direction. A width of the first protruding structure along a second direction is greater than a width of the second protruding structure along the second direction. An orthogonal projection of the first protruding structure on the first substrate is located within an orthogonal projection of a first light-shielding pattern on the first substrate.Type: ApplicationFiled: December 10, 2024Publication date: June 19, 2025Applicant: AUO CorporationInventors: Che-Min Lin, Chun-Ru Huang, Chu-Kuan Yu, Kai-Teng Chiang, FangMing Tsao, Chen-Yu Wu
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Patent number: 12314072Abstract: A voltage generating device includes a low-dropout voltage regulator and a control signal generator. The low-dropout voltage regulator provides an output voltage to a power distribution network. The low-dropout voltage regulator has a feedback circuit. The feedback circuit divides the output voltage to generate a feedback voltage according to a voltage dividing ratio, and the feedback circuit sets the voltage dividing ratio according to multiple control signals. The control signal generator is coupled to the feedback circuit and the power distribution network, and generates the control signals by comparing a sensing voltage at a reference terminal of the power distribution network with multiple threshold voltages.Type: GrantFiled: December 15, 2022Date of Patent: May 27, 2025Assignee: Windbond Electronics Corp.Inventor: Chen-Yu Wu
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Publication number: 20240371979Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: ApplicationFiled: July 16, 2024Publication date: November 7, 2024Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Patent number: 12113122Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: GrantFiled: March 3, 2023Date of Patent: October 8, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Publication number: 20240201720Abstract: A voltage generating device includes a low-dropout voltage regulator and a control signal generator. The low-dropout voltage regulator provides an output voltage to a power distribution network. The low-dropout voltage regulator has a feedback circuit. The feedback circuit divides the output voltage to generate a feedback voltage according to a voltage dividing ratio, and the feedback circuit sets the voltage dividing ratio according to multiple control signals. The control signal generator is coupled to the feedback circuit and the power distribution network, and generates the control signals by comparing a sensing voltage at a reference terminal of the power distribution network with multiple threshold voltages.Type: ApplicationFiled: December 15, 2022Publication date: June 20, 2024Applicant: Winbond Electronics Corp.Inventor: Chen-Yu Wu
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Patent number: 11899857Abstract: A touchpad module includes a base plate, a touch member, a supporting structure and a pressure sensing unit. The touch member is movable toward the base plate. The supporting structure is arranged between the base plate and the touch member. The pressure sensing unit is installed on the touch member. The pressure sensing unit is arranged between the touch member and the base plate. While the touch member is pressed in response to an external pressing force, the touch member is moved downwardly toward the base plate to compress the supporting structure. Consequently, the supporting structure is subjected to deformation, and the touch member has a displacement amount. According to the displacement amount, a magnitude of the pressing force is sensed by the pressure sensing unit, and a pressure sensing signal is outputted from the pressure sensing unit.Type: GrantFiled: March 8, 2023Date of Patent: February 13, 2024Assignee: PRIMAX ELECTRONICS LTD.Inventors: Wei-Chiang Huang, Hung-Wei Kuo, Chao-Wei Lee, Chen-Yu Wu
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Patent number: 11704949Abstract: Provided are a user verifying bicycle control system and a user verification method thereof, including a sensing module and a control module installed on a bicycle. The sensing module obtains a torque signal and an angle signal from a crank sensing component, further obtains a speed signal from a speed sensing unit, and outputs the torque signal, the angle signal, and the speed signal to the control module; the control module assembles the torque signal, the angle signal, and the speed signal into a signal sequence as a key to verify a user identity for the bicycle.Type: GrantFiled: July 21, 2021Date of Patent: July 18, 2023Assignee: SINBON Electronics Company Ltd.Inventor: Chen-Yu Wu
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Publication number: 20230207670Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: ApplicationFiled: March 3, 2023Publication date: June 29, 2023Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Patent number: 11600717Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: GrantFiled: October 13, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Publication number: 20230022298Abstract: Provided are a bicycle control system and a user verification method thereof, including a sensing module and a control module installed on a bicycle. The sensing module obtains a torque signal and an angle signal from a crank sensing component, further obtains a speed signal from a speed sensing unit, and outputs the torque signal, the angle signal, and the speed signal to the control module; the control module assembles the torque signal, the angle signal, and the speed signal into a signal sequence as a key to verify a user identity for the bicycle.Type: ApplicationFiled: July 21, 2021Publication date: January 26, 2023Inventor: CHEN-YU WU
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Publication number: 20220262755Abstract: Achieving homogeneous and heterogeneous integration for 2.5D and 3D integrated circuit, chip-to-wafer, chip-to-substrate, or wafer-to-wafer bonding is an essential technology. The landing wafer or substrate is bonded with a carrier by using a temporary bonding material before thinning the landing wafer to the desired thickness. Upon completion of redistribution layer formation, Cu pad formation, or other backside processing, dies or wafers with through-silicon vias are stacked onto the landing substrate before molding and singulation. As the landing wafer usually has interconnection metals in the bond line, and those interconnection metals are typically made from lead-free solder alloys, deformation of those solder alloys during thermocompression bonding becomes an issue for manufacturers. To address this issue, a polymeric material with desired strengths is coated on the device wafer to form a conformal protective layer on top of solder alloys, thus enabling temporary bonding and debonding processes.Type: ApplicationFiled: February 15, 2022Publication date: August 18, 2022Inventors: Chia-Hsin Lee, Alice Guerrero, Arthur O. Southard, Chen-Yu Wu, Xiao Liu
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Publication number: 20210367059Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: ApplicationFiled: October 13, 2020Publication date: November 25, 2021Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Patent number: 11088677Abstract: A signal receiving device includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage and a bias voltage. The first amplifier generates a first common current based on the bias voltage and, based on the first common current, generates a first output signal and a second output signal complementary to each other by comparing the input signal and the reference voltage. The duty cycle adjuster charges and discharges a selected capacitor according to the first output signal or the second output signal to generate a sensing voltage, and generates a common reference voltage according to the sensing voltage. The common mode feedback circuit generates the bias voltage by comparing the common reference voltage and the reference voltage.Type: GrantFiled: November 27, 2020Date of Patent: August 10, 2021Assignee: Winbond Electronics Corp.Inventors: Chen-Yu Wu, Chun-Cheng Chen
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Publication number: 20160054651Abstract: The present invention relates to a photosensitive resin composition for a black matrix and an application thereof. The aforementioned photosensitive resin composition includes an alkali-soluble resin (A), a compound having an ethylenically unsaturated group (B), a photo-initiator (C), a solvent (D), a black pigment (E) and an oxetane compound having silicon atom (F). The aforementioned alkali-soluble resin (A) includes a first alkali-soluble resin (A-1) having a fluorine atom. The photosensitive resin composition for the black matrix has excellent development resistance and lower surface resistance.Type: ApplicationFiled: November 5, 2015Publication date: February 25, 2016Inventors: Chun-An Shih, Hao-Wei Liao, Li-Ting Hsieh, Chen-Yu Wu
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Patent number: 9058760Abstract: An adjusting method includes steps of providing a display apparatus, transforming a first value in a first color space of a color displayed by the display apparatus into a second value in a second color space, adjusting the second value to a third value in the second color space, and transforming the third value into a fourth value in the first color space. By adjusting the second value to the third value in the second color space intuitively, the present invention achieves the advantages of providing an intuitive operation, simplifying the adjustment, saving time and enhancing the user experiences.Type: GrantFiled: March 12, 2013Date of Patent: June 16, 2015Assignee: DELTA ELECTRONICS, INC.Inventors: Chung-Yi Yang, Bor Wang, Chen-Yu Wu
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Publication number: 20140279869Abstract: A PDM system, method, and computer program product for data transfer. A method includes determining a plurality of persistent objects in a data structure to be replicated to a plurality of replication sites. The plurality of persistent objects is identified based on a transaction table entry identifying a specific scoped transaction. The method includes determining specific persistent objects of the plurality of persistent objects to be replicated to each of the plurality of replication sites based on which of the plurality of persistent objects have been updated since last being replicated to each respective replication site, without traversing the full data structure. The method includes initiating a synchronization transaction according to the specific persistent objects and replicating the specific persistent objects to at least one of the plurality of replication sites, without traversing the full data structure.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: Siemens Product Lifecycle Management Software Inc.Inventors: Chen-Yu Wu, Reiner K. Kaiser