Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and an active area, a second anti-fuse structure including a second dielectric layer between a second gate conductor and the active area, and a first pair of conductive segments electrically connected to the first and second gate conductors and aligned along a row direction perpendicular to a column direction of the first and second gate conductors. The active area is included in a plurality of active areas, the first pair of conductive segments is included in a plurality of pairs of conductive segments, and adjacent pairs of conductive segments of the plurality of pairs of conductive segments are separated by a total of two active areas of the plurality of active areas.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: In an approach, a processor obtains a configuration file of a distributed file system federation, the configuration file comprising a list of a plurality of subclusters within the distributed file system federation and migration trigger factors for the plurality of subclusters. A processor determines a list of one or more source subclusters and a list of to-be-migrated directories in the one or more source subclusters based on a scanning result of the plurality of subclusters and the migration trigger factors in the configuration file. A processor generates a migration plan to migrate the to-be-migrated directories from the one or more source subclusters to one or more target subclusters in the distributed file system federation.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

Abstract: A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

Abstract: An approach is provided for optimizing a feedback-type question answering process. A training set is constructed to detect missing information of a question. A natural language generation model is trained using the missing information. The natural language generation model is executed to generate a rhetorical question. A response to the rhetorical question is combined with the question to generate an input to a language processor. A new question is generated. The new question is applied to a document library. A final answer is generated.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.