Patents by Inventor Chenyue Ma

Chenyue Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230327018
    Abstract: An integrated MOSFET-JFET device made from a Silicon-Carbide (SiC) wafer has N+ source, P body diode, and upper N regions that form vertical MOSFETs on the sidewalls of polysilicon gates. An N substrate under the upper N region forms a drift region that is pinched by the JFET to limit saturation current. Trenches are formed between MOSFETs. JFETs are formed by doping the bottom and sidewalls of the trenches to form P+ taps to the N substrate. P islands within the N substrate are formed underneath the P+ taps. These P islands are wider near the surface but are successively narrower with increased vertical spacing deeper into the N substrate. This P-island tapering provides a tapered shape to the JFET depletion region that pinches the MOSFET drift region in the N substrate to limit saturation current and yet reduce linear-region ON resistance.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Shu Kin YAU, Chenyue MA, Siu Wai WONG
  • Patent number: 10885256
    Abstract: An existing layout of an Integrated Circuit (IC) is migrated to two or more target layouts for different semiconductor processes with different design rules. The existing layout file is parsed for data items such as boundaries, paths, text, and cell instances to generate a layout database file with a text format. A layout engineer selects functions from a layout design toolkit and writes reusable code with these functions. Placement functions can specify relative locations to other data items that are dependent on the design rules. Routing functions allow interconnect to be re-routed after placements are adjusted for various target design rules. An analog layout expertise integrator replaces some of the data items in the layout database file with the reusable code to generate a reusable layout database. A layout generator compiles the reusable layout database and converts it to multiple target layouts for multiple design rules.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: January 5, 2021
    Inventors: Yuan Lei, Chenyue Ma
  • Patent number: 10665584
    Abstract: A well-less Transient Voltage Suppressor (TVS) Silicon-Controlled Rectifier (SCR) has a P+ anode region that is not in an N-well. The P+ anode region 20 is surrounded by N+ isolation regions near the surface, and a deep N+ region underneath that is formed in a p-substrate. A N+ cathode region is formed in the p-substrate. The deep N+ region has a doping of 5×1018 to 5×1019/cm3, compared to a doping of 1×1016/cm3 for a typical N-well, or a doping of 1×1013 to 1×1015/cm3 for the p-substrate. The high doping in the deep N+ region causes a recombination current that can shunt half of the anode current. Since the deep N+ region is much shallower than an N-well, the sidewall capacitance is greatly reduced, allowing for higher speed applications.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 26, 2020
    Assignee: Hong Kong Applied Science and Technology Research Insstitute Company, Limited
    Inventors: Chenyue Ma, Chun-Kit Yam, Xiao Huo
  • Patent number: 10504886
    Abstract: An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 10, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Chun-Kit Yam, Chenyue Ma, Shuli Pan