Patents by Inventor Chenyun Pan

Chenyun Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11043592
    Abstract: An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 22, 2021
    Assignee: Georgia Tech Research Corporation
    Inventors: Azad Naeemi, Chenyun Pan
  • Publication number: 20200058795
    Abstract: An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 20, 2020
    Inventors: Azad Naeemi, Chenyun Pan
  • Patent number: 10177769
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 8, 2019
    Assignee: Georgia Tech Research Corporation
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Patent number: 10164641
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 25, 2018
    Assignee: Georgia Tech Research Corporation
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180248553
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180248554
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Patent number: 9979401
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 22, 2018
    Assignee: Georgia Tech Research Corporation
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180026645
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 25, 2018
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi