Patents by Inventor Cheok-Kei LEI
Cheok-Kei LEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907633Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
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Publication number: 20240037309Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: ApplicationFiled: June 30, 2023Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Publication number: 20230334208Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei LEI, Zhe-Wei JIANG, Chi-Yu LU, Yi-Hsin KO, Chi-Lin LIU, Hui-Zhong ZHUANG
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Patent number: 11734481Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: GrantFiled: May 17, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Patent number: 11694012Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: GrantFiled: June 29, 2022Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Publication number: 20230090213Abstract: A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.Type: ApplicationFiled: November 30, 2022Publication date: March 23, 2023Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
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Patent number: 11526649Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.Type: GrantFiled: March 8, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
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Publication number: 20220382948Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
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Patent number: 11494543Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.Type: GrantFiled: May 26, 2020Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
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Publication number: 20220327275Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Patent number: 11392743Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: GrantFiled: May 26, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Publication number: 20210271794Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Publication number: 20210200927Abstract: A system and method for transistor placement in a standard cell layout includes identifying a plurality of transistors in a circuit. A drain terminal of each of the plurality of transistors is connected to an output of the circuit. The system and method also include determining that a first transistor and a second transistor of the plurality of transistors satisfy a merging priority, combining an active region of the first transistor and the second transistor to form a mega transistor having a common active region, and replacing the first transistor and the second transistor in the standard cell layout of the circuit with the mega transistor. The common active region combines the active region of a first drain terminal of the first transistor and a second drain terminal of the second transistor.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Inventors: Cheok-Kei Lei, Chi-Lin Liu, Yu-Lun Ou, Chien-Hsing Li, Zhe-Wei Jiang, Hui-Zhong Zhuang
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Publication number: 20210192118Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
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Patent number: 11030368Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: GrantFiled: May 22, 2020Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Patent number: 10943050Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.Type: GrantFiled: July 17, 2019Date of Patent: March 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
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Publication number: 20200395938Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: ApplicationFiled: May 26, 2020Publication date: December 17, 2020Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Publication number: 20200285792Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei LEI, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chi-Yu LU, Yi-Hsin KO
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Publication number: 20200285797Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
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Patent number: 10691849Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: GrantFiled: February 28, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko