Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.

Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.

Abstract: An apparatus and a method for determining careless driving are provided and determine more reliable careless driving by generating normal driving patterns using driving performance data for a reference time at the beginning of driving. In addition, careless driving patterns greater than a predetermined number are detected using the normal driving pattern and a boundary between the normal driving and the careless driving is determined using a supervised learning method. The careless driving of the driver is then determined based on the determined boundary.

Abstract: A driving concentration level calculating apparatus is provided and includes a controller configured to acquire an acceleration of a traveling vehicle and measure a relative velocity to a preceding vehicle. In addition, noise is removed from the acquired acceleration of the traveling vehicle and from the measured relative velocity to the preceding vehicle. A plurality of correlation values are calculated based on the acceleration of the traveling vehicle and the relative velocity to the preceding vehicle from which noise has been removed. In addition, the controller is configured to detect a time at which a maximum correlation value is calculated as a driving concentration level from among the calculated correlation values.

Abstract: An apparatus and a method for determining careless driving are provided and determine more reliable careless driving by generating normal driving patterns using driving performance data for a reference time at the beginning of driving. In addition, careless driving patterns greater than a predetermined number are detected using the normal driving pattern and a boundary between the normal driving and the careless driving is determined using a supervised learning method. The careless driving of the driver is then determined based on the determined boundary.

Abstract: A driving concentration level calculating apparatus is provided and includes a controller configured to acquire an acceleration of a traveling vehicle and measure a relative velocity to a preceding vehicle. In addition, noise is removed from the acquired acceleration of the traveling vehicle and from the measured relative velocity to the preceding vehicle. A plurality of correlation values are calculated based on the acceleration of the traveling vehicle and the relative velocity to the preceding vehicle from which noise has been removed. In addition, the controller is configured to detect a time at which a maximum correlation value is calculated as a driving concentration level from among the calculated correlation values.

Abstract: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal.

Abstract: A driving integrated circuit and methods thereof are provided. The driving IC includes a memory for driving a display panel and having a memory structure including at least one cell block, a scan register receiving data read from the memory, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block. One method includes performing a read operation to read data from a memory, the read operation including sensing and amplifying data stored within a memory cell, turning on a switch to increase a bit line voltage above a voltage threshold and latching the amplified data received through a line connected to the switch and transmitting the read data to the panel of the display device.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.

Abstract: An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature.

Abstract: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.

Abstract: A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.

Abstract: An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature.

Abstract: An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block configured to output data, selected by a second column select signal on a second scan output line if the first memory block is determined to be non-defective, the second memory block further configured to output data, selected by the first column select signal, on the first scan output line if the first memory block is determined to be defective.

Abstract: A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.

Abstract: A driving integrated circuit (IC) and methods thereof are provided. The example driving IC may include a memory storing data for driving a panel of a display device and having a memory structure including at least one cell block, a scan register receiving data read from the memory and latching the received read data, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit selectively establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block, the activated cell block included among the at least one cell block of the memory.

Abstract: An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block configured to output data, selected by a second column select signal on a second scan output line if the first memory block is determined to be non-defective, the second memory block further configured to output data, selected by the first column select signal, on the first scan output line if the first memory block is determined to be defective.

Abstract: Integrated circuit memory devices include a stress voltage generator that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during the stress BIST of the memory cell array. The stress voltage generator is preferably responsive to a BIST request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a BIST of the memory cell array. The stress voltage generator is responsive to the BIST request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform a BIST of the memory cell array. Accordingly, circuits within the integrated circuit memory device can be responsive to external test signals to generate stress voltages during BIST.

Abstract: A merged memory logic (MML) integrated circuit includes an adjustable clock generator configured to receive a input clock signal and produce an adjustably delayed clock signal therefrom responsively to a control signal generated by a programmable logic circuit. A buffer has a clock input for receiving the adjustably delayed clock signal and is configured to receive an input data signal and produce a corresponding output data signal therefrom responsive to the adjustably delayed clock signal. The adjustable clock generator preferably includes a clock generator configured to receive the input clock signal and produce a output clock signal therefrom, and an adjustable delay circuit which receives the output clock signal and generates the adjustably delayed clock signal therefrom, the adjustably delayed clock signal being delayed by a selected one of a plurality of selectable delay intervals with respect to the output clock signal.