Abstract: A method for driving in a blind spot of a sensor mounted on an autonomous vehicle is provided. The method includes steps of: a computing device of the autonomous vehicle running on a specific road locating the autonomous vehicle from precision map information, sensor information and GPS information, and in response to determining that the autonomous vehicle is expected to encounter a specific event, transmitting vehicle location data, travelling direction data, vehicle structure data and sensor location data and sensor's viewing angle data to the server, to determine whether a region of interest corresponding to the specific event is included in blind spot candidates; receiving blind spot stereoscopic data, computed from the data received from the autonomous vehicle and 3D occlusion environmental data corresponding to occluding static objects in the blind spot candidates, from the server; and controlling movement of the autonomous vehicle based on the blind spot stereoscopic data.

Abstract: An exemplary embodiment provides an intruder detection method capable of accurately detecting an intruder and estimating an abnormal behavior of the intruder even when viewpoints of acquired images are different from each other. An intruder detection method is suitable for being performed by an intruder detection device for detecting an intruder based on images and includes: receiving input images acquired by multiple cameras; extracting feature maps associated with a plurality of viewpoints by applying the input images to a plurality of convolutional neural networks provided separately for the plurality of viewpoints of the images; and detecting the intruder based on the feature maps associated with the plurality of viewpoints.

Abstract: A single-atom catalyst structure comprises: a three-dimensional ordered mesoporous carbon structure; and a single-atom catalyst doped inside the three-dimensional ordered mesoporous carbon structure, wherein the single-atom catalyst may comprise transition metal, nitrogen, and carbon. In an alternative implementation, a single-atom catalyst structure comprises: a three-dimensional ordered mesoporous carbon structure; and a single-atom catalyst doped inside the three-dimensional ordered mesoporous carbon structure, wherein the single-atom catalyst includes transition metal, nitrogen, and carbon.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

Abstract: A shoe outsole dispensing apparatus having a dispenser located above the conveyor carrying adhesive-coated shoe outsoles that are classified into left outsoles and right outsoles and that are dispensed such that the left outsoles to a first side of the conveyor and the right outsoles to a second side of the conveyor is provided. A controller controls the operation of the dispenser. As a result of the outsoles coated with adhesive being automatically classified as left and right outsoles by the dispenser, and the outsoles are dispensed on opposite sides of the conveyor carrying the outsoles, this has the result that productivity of assembling shoes greatly increased as a result of the ability to dispose outsoles very quickly compared to the prior art operation of manually sorting the outsoles, and also the occurrence of shoe defects due to manual errors may be prevented, thus enhancing shoe quality.

Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

Abstract: A shoe outsole dispensing apparatus having a dispenser located above the conveyor carrying adhesive-coated shoe outsoles that are classified into left outsoles and right outsoles and that are dispensed such that the left outsoles to a first side of the conveyor and the right outsoles to a second side of the conveyor is provided. A controller controls the operation of the dispenser. As a result of the outsoles coated with adhesive being automatically classified as left and right outsoles by the dispenser, and the outsoles are dispensed on opposite sides of the conveyor carrying the outsoles, this has the result that productivity of assembling shoes greatly increased as a result of the ability to dispose outsoles very quickly compared to the prior art operation of manually sorting the outsoles, and also the occurrence of shoe defects due to manual errors may be prevented, thus enhancing shoe quality.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

Abstract: Disclosed relates to a driving support apparatus including at least: a detection unit that detects a driving lane on which a user's vehicle and a front vehicle located in front of the user's vehicle are driving based on image data output from a camera; a first calculation unit that calculates a second front vehicle width for the front vehicle based on a first front vehicle width for the front vehicle measured on the image data, a first driving lane width for the driving lane measured on the image data, and a second driving lane width predetermined according to a characteristic of the driving lane; and a second calculation unit that calculates a distance from the front vehicle based on a focal length of the camera, the first front vehicle width, and the second front vehicle width, thereby precisely measuring the distance from the front vehicle based on camera image data.

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

Abstract: A vehicle seat lumbar support including: brackets located on both sides of a seat back frame; a fixing unit having guides for guiding an operating unit and a driver including a motor having a driving shaft, a worm fitted to the driving shaft of the motor, a worm gear rotating by the worm, and a pinion gear fitted to a shaft of the worm gear; and an operating unit driven by the driver and including a block band having base blocks having hooks formed on underside surfaces thereof, a base band for locking the hooks of the base blocks thereonto in such a manner as to be coupled to the guides on top and underside of one side thereof, and a rack gear formed on the base band in such a manner as to engage with the pinion gear fitted to the shaft of the worm gear.

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode.

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.