Patents by Inventor Cheol Ho Joh

Cheol Ho Joh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110189928
    Abstract: A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive is member is disposed at the first region. The second adhesive member is disposed at the third region.
    Type: Application
    Filed: March 17, 2011
    Publication date: August 4, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE
  • Patent number: 7859108
    Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: December 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Woong Sun Lee, Il Hwan Cho, Myung Geun Park, Cheol Ho Joh, Eun Hye Do, Ki Young Kim, Ji Eun Kim, Jong Hyun Nam
  • Patent number: 7705468
    Abstract: A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: April 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cheol Ho Joh
  • Publication number: 20100092718
    Abstract: A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive member is disposed at the first region. The second adhesive member is disposed at the third region.
    Type: Application
    Filed: December 30, 2008
    Publication date: April 15, 2010
    Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE
  • Publication number: 20090140426
    Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.
    Type: Application
    Filed: December 27, 2007
    Publication date: June 4, 2009
    Inventors: Woong Sun LEE, Il Hwan CHO, Myung Geun PARK, Cheol Ho JOH, Eun Hye DO, Ki Young KIM, Ji Eun KIM, Jong Hyun NAM
  • Publication number: 20090096075
    Abstract: A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads.
    Type: Application
    Filed: November 15, 2007
    Publication date: April 16, 2009
    Inventor: Cheol Ho JOH
  • Publication number: 20080061406
    Abstract: A semiconductor package includes a semiconductor chip; and an encapsulant for covering the semiconductor chip, such that the encapsulant includes a molding part for covering the semiconductor chip to protect the semiconductor chip from the external environment; and an electromagnetic shielding part for covering an outer surface of the molding part and containing therein electrically conductive particles for shielding an electromagnetic wave radiated from the semiconductor chip to the outside and an electromagnetic wave incident from the outside to the semiconductor chip.
    Type: Application
    Filed: June 8, 2007
    Publication date: March 13, 2008
    Inventor: Cheol Ho JOH
  • Publication number: 20040262773
    Abstract: The present invention discloses a chip-stacked package is disclosed. The chip-stacked package comprises: a doubly down-set leadframe having a down-set tip to be wire-bonded; a first semiconductor chip attached under the down-set tip of the leadframe; a first metal wire electrically connecting bonding pads of the first semiconductor chip with the down-set tip of the leadframe; a second semiconductor chip attached on the leadframe; a second metal wire electrically connecting the second semiconductor chip with the leadframe; and an epoxy molding compound encapsulating the first and second semiconductor chips, the first and second metal wires, and a portion of the leadframe while exposing the backside of the first semiconductor chip. According to the present invention, since the chip-stacked package is manufactured using the general LOC leadframe, a manufacturing process thereof can be simplified as compared to the existing chip-stacked package.
    Type: Application
    Filed: November 4, 2003
    Publication date: December 30, 2004
    Inventors: Cheol Ho Joh, Qwan Ho Chung