Patents by Inventor Cheol-Hui Ryu

Cheol-Hui Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for decoding LDPC code based on prototype parity check matrixes
    Patent number: 8214717
    Abstract: Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: July 3, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Ee Oh, Chanho Yoon, Cheol-Hui Ryu, Eun-Young Choi, Sok-Kyu Lee
  • APPARATUS AND METHOD FOR DECODING LDPC CODE BASED ON PROTOTYPE PARITY CHECK MATRIXES
    Publication number: 20090158121
    Abstract: Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.
    Type: Application
    Filed: July 2, 2008
    Publication date: June 18, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jong-Ee OH, Chanho YOON, Cheol-Hui RYU, Eun-Young CHOI, Sok-Kyu LEE