Patents by Inventor Cheol-Hwi Ryu
Cheol-Hwi Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10128026Abstract: A superconducting wire having improved electrical and physical properties.Type: GrantFiled: June 23, 2016Date of Patent: November 13, 2018Assignee: LS CABLE & SYSTEM LTD.Inventors: Jin Bae Na, Young Woong Kim, Chang Youl Choi, Cheol Hwi Ryu, Seok Ju Lee
-
Publication number: 20180182513Abstract: The present invention relates to a superconducting wire having improved electrical and physical properties.Type: ApplicationFiled: June 23, 2016Publication date: June 28, 2018Inventors: Jin Bae NA, Young Woong KIM, Chang Youl CHOI, Cheol Hwi RYU, Seok Ju LEE
-
Patent number: 9002423Abstract: A superconducting cable is provided. The superconducting cable includes a core part including a former disposed at the center of the core part, one or more superconducting conductive layers with each electric phase disposed at the outside of the former in a radial directions, a insulating layer disposed at the outside of each the conductive layer in a radial direction and a shielding layer disposed at the outermost of the insulating layer; and a cryostat disposed at the outside of the core part in a radial direction with first space being interposed therebetween, having a vacuum part disposed therein and electrically wired to neutral pole (N pole).Type: GrantFiled: October 23, 2012Date of Patent: April 7, 2015Assignee: LS Cable Ltd.Inventors: Hyun Man Jang, Su Kil Lee, Young Woong Kim, Cheol Hwi Ryu
-
Publication number: 20130165324Abstract: A superconducting cable is provided. The superconducting cable includes a core part including a former disposed at the center of the core part, one or more superconducting conductive layers with each electric phase disposed at the outside of the former in a radial directions, a insulating layer disposed at the outside of each the conductive layer in a radial direction and a shielding layer disposed at the outermost of the insulating layer; and a cryostat disposed at the outside of the core part in a radial direction with first space being interposed therebetween, having a vacuum part disposed therein and electrically wired to neutral pole (N pole).Type: ApplicationFiled: October 23, 2012Publication date: June 27, 2013Inventors: Hyun Man Jang, Su Kil Lee, Young Woong Kim, Cheol Hwi Ryu
-
Patent number: 8404543Abstract: A method for fabricating a semiconductor device with a buried gate includes: etching a substrate to form a plurality of trenches; forming a plurality of buried gates that fill lower portions of the trenches; forming a plurality of sealing layers that gap-fill upper portions of the trenches and have protrusions higher than a top surface of the substrate; forming an inter-layer insulation layer over the whole surface of the substrate including the sealing layers; and etching the inter-layer insulation layer to form a contact hole that is aligned with a space between the protrusions of the sealing layers.Type: GrantFiled: November 23, 2009Date of Patent: March 26, 2013Assignee: Hynix Semiconductor Inc.Inventors: Jong-Han Shin, Cheol-Hwi Ryu, Sung-Jun Kim
-
Patent number: 8384135Abstract: A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: GrantFiled: June 20, 2011Date of Patent: February 26, 2013Assignee: SK hynix Inc.Inventors: Cheol Hwi Ryu, Hyung Soon Park, Jong Han Shin, Jum Yong Park, Sung Jun Kim
-
Patent number: 8314030Abstract: A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.Type: GrantFiled: June 23, 2009Date of Patent: November 20, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Jum-Yong Park, Noh-Jung Kwak, Yong-Soo Choi, Cheol-Hwi Ryu
-
Publication number: 20110240950Abstract: A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Cheol Hwi Ryu, Hyung Soon Park, Jong Han Shin, Jum Yong Park, Sung Jun Kim
-
Patent number: 7994056Abstract: A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.Type: GrantFiled: December 27, 2007Date of Patent: August 9, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jong-Han Shin, Hyung-Soon Park, Cheol-Hwi Ryu, Jum-Yong Park, Sung-Jun Kim
-
Patent number: 7981797Abstract: A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: GrantFiled: June 25, 2008Date of Patent: July 19, 2011Assignee: Hynix Semiconductor Inc.Inventors: Cheol-Hwi Ryu, Hyung-Soon Park, Jong-Han Shin, Jum-Yong Park, Sung-Jun Kim
-
Publication number: 20100330775Abstract: A method for fabricating a semiconductor device with a buried gate includes: etching a substrate to form a plurality of trenches; forming a plurality of buried gates that fill lower portions of the trenches; forming a plurality of sealing layers that gap-fill upper portions of the trenches and have protrusions higher than a top surface of the substrate; forming an inter-layer insulation layer over the whole surface of the substrate including the sealing layers; and etching the inter-layer insulation layer to form a contact hole that is aligned with a space between the protrusions of the sealing layers.Type: ApplicationFiled: November 23, 2009Publication date: December 30, 2010Inventors: Jong-Han SHIN, Cheol-Hwi RYU, Sung-Jun KIM
-
Publication number: 20100184359Abstract: A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.Type: ApplicationFiled: June 23, 2009Publication date: July 22, 2010Inventors: Jum-Yong Park, Noh-Jung Kwak, Yong-Soo Choi, Cheol-Hwi Ryu
-
Publication number: 20090127653Abstract: A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: ApplicationFiled: June 25, 2008Publication date: May 21, 2009Applicant: Hynix Semiconductor, Inc.Inventors: Cheol Hwi RYU, Hyung Soon PARK, Jong Han SHIN, Jum Yong PARK, Sung Jun KIM
-
Publication number: 20090117739Abstract: A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.Type: ApplicationFiled: December 27, 2007Publication date: May 7, 2009Applicant: Hynix Semiconductor Inc.Inventors: Jong-Han Shin, Hyung-Soon Park, Cheol-Hwi Ryu, Jum-Yong Park, Sung-Jun Kim
-
Patent number: 7507657Abstract: Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with the present invention, a chemical mechanical polishing (CMP) process that is the last process of the storage node contact isolation process is performed by using the slurry without the selectivity or the reverse selectivity, thereby removing the plurality of cruspidal patterns at every interface of the plurality of bit line patterns BL and the plurality of storage node contacts.Type: GrantFiled: June 9, 2005Date of Patent: March 24, 2009Assignee: Hynix Semiconductor, Inc.Inventors: Cheol-Hwi Ryu, Jong-Han Shin
-
Publication number: 20080102626Abstract: A semiconductor package includes method of forming a copper wiring may comprise forming an interlayer insulation film provided with a damascene pattern for wiring over a semiconductor substrate; depositing a barrier metal film over a surface of the damascene pattern and the interlayer insulation film; depositing a copper film over the barrier metal film so as to fill the damascene pattern; and performing an electrochemical mechanical polishing by using a fixed-abrasive pad, supplying an electrolyte solution, and applying an electric field so as to expose the interlayer insulation film.Type: ApplicationFiled: July 11, 2007Publication date: May 1, 2008Inventors: Cheol Hwi RYU, Hyung Soon PARK, Jong Han SHIN, Jum Yong PARK, Sung Jun KIM
-
Publication number: 20060141770Abstract: Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with the present invention, a chemical mechanical polishing (CMP) process that is the last process of the storage node contact isolation process is performed by using the slurry without the selectivity or the reverse selectivity, thereby removing the plurality of cruspidal patterns at every interface of the plurality of bit line patterns BL and the plurality of storage node contacts.Type: ApplicationFiled: June 9, 2005Publication date: June 29, 2006Inventors: Cheol-Hwi Ryu, Jong-Han Shin