Abstract: An image processing device includes a target pixel detector configured to detect a plurality of target pixels in which noise is generated among a plurality of pixels included in an image sensor. The image processing device also includes a target pixel corrector configured to change target pixel values, which are pixel values of the plurality of target pixels, by using average pixel values of neighboring pixels included in a preset range based on a position of each of the plurality of target pixels. The image processing device further includes a target pixel compensator configured to compensate for the target pixel values by using an accumulation value obtained by accumulating values corresponding to a decimal fraction part of the average pixel values.

Abstract: Disclosed is an image sensing device including a plurality of defect detectors each suitable for detecting whether a corresponding target image value is defective, and generating detection information corresponding to a result of the detection, a defect scheduler suitable for sequentially outputting one or more defective image values, which are the target image values detected as defective among the plurality of target image values, based on the detection information, and a defect corrector suitable for correcting the output defective image values.

Abstract: An image processing device includes a target pixel detector configured to detect a plurality of target pixels in which noise is generated among a plurality of pixels included in an image sensor. The image processing device also includes a target pixel corrector configured to change target pixel values, which are pixel values of the plurality of target pixels, by using average pixel values of neighboring pixels included in a preset range based on a position of each of the plurality of target pixels. The image processing device further includes a target pixel compensator configured to compensate for the target pixel values by using an accumulation value obtained by accumulating values corresponding to a decimal fraction part of the average pixel values.

Abstract: Disclosed is an image sensing device including a plurality of defect detectors each suitable for detecting whether a corresponding target image value is defective, and generating detection information corresponding to a result of the detection, a defect scheduler suitable for sequentially outputting one or more defective image values, which are the target image values detected as defective among the plurality of target image values, based on the detection information, and a defect corrector suitable for correcting the output defective image values.

Abstract: Disclosed is an image sensing device including an image sensor suitable for generating image values corresponding to a captured image, and an image processor suitable for analyzing a texture of a target kernel of the captured image based on a first image value corresponding to a center of the target kernel and second image values corresponding to a periphery of the target kernel among it mage values of the target kernel.

Abstract: An image sensing device includes an image sensor including a first sub-pixel array and a second sub-pixel array. The first sub-pixel array includes a plurality of first pixels having a first color filter, and the second sub-pixel array includes a plurality of second pixels having a second color filter and a plurality of third pixels for phase detection. The image sensor may generate first pixel values from the first pixels, second pixel values from the second pixels and third pixel values from the third pixels. The image sensing device also includes an image processor suitable for generating a first image value corresponding to the first sub-pixel array based on the first pixel values and generating a second image value corresponding to the second sub-pixel array based on the first to third pixel values.

Abstract: An image sensing device includes an image sensor including a first sub-pixel array and a second sub-pixel array. The first sub-pixel array includes a plurality of first pixels having a first color filter, and the second sub-pixel array includes a plurality of second pixels having a second color filter and a plurality of third pixels for phase detection. The image sensor may generate first pixel values from the first pixels, second pixel values from the second pixels and third pixel values from the third pixels. The image sensing device also includes an image processor suitable for generating a first image value corresponding to the first sub-pixel array based on the first pixel values and generating a second image value corresponding to the second sub-pixel array based on the first to third pixel values.

Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.

Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.

Abstract: A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.

Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die perpendicular to the first die, determining a first bound region including a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die, calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.

Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated.

Abstract: A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.