Abstract: A high quality asphalt containing pitch is generated as a by-product in a solvent deasphalting process and a method of preparing the same. The pitch is obtained by subjecting a mixture comprising a first vacuum residue and a first petroleum distillate, which is lighter than the vacuum residue and has high amounts of aromatic and resin, to solvent deasphalting. The operation conditions of the solvent deasphalting process are appropriately controlled, such that aromatic and resin components contained in the atmospheric residue and vacuum residue can be distributed to the pitch, and as well, a saturate can be removed.

Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.

Abstract: A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region.

Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift region. A source region of the second conductivity is in the body region. A gate extends over a surface portion of the body region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor. A drain region of the second conductivity type is in the drift region. The drain region is laterally spaced from the body region. A first buried layer of the second conductivity type is between the substrate and drift region. The first buried layer laterally extends from under the body region to under the drain region. A second buried layer of the first conductivity type is between the first buried layer and the drift region.

Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.

Abstract: Power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage and a method for manufacturing the power devices are described.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device having a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, and P-type and N-type resistors are disclosed. In one embodiment, a photoresist pattern is formed on a pad oxide layer and field oxides on an N-type epitaxial layer that is grown on a P-type semiconductor substrate. The pad oxide layer is etched after implanting P-type impurity into the epitaxial layer by using the photoresist pattern as a mask. Deposition of a polysilicon layer after removing the photoresist pattern is followed by implanting P-type impurity and N-type impurity into the polysilicon layer in sequence. Another photoresist pattern formed on the polysilicon layer after the previous implantation is used as an etch mask for etching the polysilicon layer to form polysilicon electrodes of transistors and P-type and N-type resistors as well as expose the surface of the epitaxial layer near an emitter region of the vertical transistor.

Abstract: Power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage and a method for manufacturing the power devices are described.

Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift region. A source region of the second conductivity is in the body region. A gate extends over a surface portion of the body region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor. A drain region of the second conductivity type is in the drift region. The drain region is laterally spaced from the body region. A first buried layer of the second conductivity type is between the substrate and drift region. The first buried layer laterally extends from under the body region to under the drain region. A second buried layer of the first conductivity type is between the first buried layer and the drift region.

Abstract: A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device having a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, and P-type and N-type resistors are disclosed. In one embodiment, a photoresist pattern is formed on a pad oxide layer and field oxides on an N-type epitaxial layer that is grown on a P-type semiconductor substrate. The pad oxide layer is etched after implanting P-type impurity into the epitaxial layer by using the photoresist pattern as a mask. Deposition of a polysilicon layer after removing the photoresist pattern is followed by implanting P-type impurity and N-type impurity into the polysilicon layer in sequence. Another photoresist pattern formed on the polysilicon layer after the previous implantation is used as an etch mask for etching the polysilicon layer to form polysilicon electrodes of transistors and P-type and N-type resistors as well as expose the surface of the epitaxial layer near an emitter region of the vertical transistor.

Abstract: A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

Abstract: A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

Abstract: A complementary bipolar transistor having a lateral npn bipolar trasistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

Abstract: A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.

Abstract: A semiconductor device and a method for manufacturing such a device are presented. The type of semiconductor device is one which merges one type of transistor (e.g., bipolar junction transistors) with another type (e.g., CMOS transistors). Specifically, the semiconductor device may comprise a semiconductor substrate and first buried layers of a first conductive and second type buried layers of a second conductive type both formed within the semiconductor substrate. The first buried layers are preferably at a different level within the semiconductor substrate then the level of the second buried layers. First epitaxial layer portions are formed over the first buried layers and second epitaxial layer portions are formed over the second type buried layers. Isolation regions are formed on the first epitaxial layer portions. In forming the semiconductor substrate, photoresists are formed at regular spatial intervals on a substrate.