Abstract: A connector assembly according to the present invention comprises a receptacle connector and a plug connector vertically coupled to the receptacle connector, the plug connector including: a signal pin having one side in electrical contact with a signal line of a cable and the other side in elastic contact with a clip pin of the receptacle connector; a shield can formed to enclose the signal pin such that the other side of the signal pin is exposed downwards and to be electrically spaced apart from the signal pin; a first insulating member coupled to the signal pin to insulate between the signal pin and the shield can; and a plug shell which has an open lower portion and encloses an upper surface and a side surface of the shield can to expose the other side of the signal pin downwards, the receptacle connector including: a clip pin which has a lower portion in contact with a signal pad of a circuit board and an upper portion in elastic contact with the other side of the signal pin; a receptacle base which is f

Abstract: An etching composition may include an oxidizer, an ammonium salt, an aqueous solvent, and an accelerator. A method of etching a metal-containing film may be performed using the etching composition, and a method of manufacturing a semiconductor device may be performed using the etching composition.

Abstract: Provided are a resist composition and a pattern forming method using the same. The resist composition includes a polymer including a first repeating unit repeating unit Formula 1, a photoacid generator, and an organic solvent. In Formula 1, L11 to L13, a11 to a13, A11 to A13, R11 to R14, b12 to b14, and p are the same as described in the detailed description.

Abstract: An etching composition for a titanium-containing layer may include an oxidant, an inorganic acid, and a selective etching inhibitor. The inorganic acid may include phosphorus-based inorganic acid, chlorine-based inorganic acid, or fluorine-based inorganic acid, or any combination thereof. The selective etching inhibitor may include a polymer having a nitrogen-containing repeating unit.

Abstract: Disclosed are a polycarboxylate compound represented by Formula 1 below, a resist composition including the same, and a method of forming a pattern using the same. In Formula 1, A11, X11, m11, n11, R13 and b13 are as described in the specification.

Abstract: An asymmetric fusion protein in which a fragment of an antibody binding to an insulin receptor, an iduronate-2-sulfatase (IDS) enzyme, and an Fc region are fused, and a use thereof are disclosed. The fusion protein can cross the blood-brain barrier (BBB) to deliver the IDS enzyme to the brain. Therefore, a pharmaceutical composition containing the fusion protein as an active ingredient can be used as a therapeutic agent for a central nervous system disease and particularly, is expected to prevent and treat various diseases caused by ribosome accumulation.

Abstract: The present disclosure relates to a zinc plated steel sheet having excellent fatigue strength of electrical resistance spot welds and a method for manufacturing the same. According to an aspect of the present disclosure, a zinc plated steel sheet includes a base steel sheet and a zinc-based plating layer formed on a surface of the base steel sheet, wherein a concentration profile of one or two of oxygen, and silicon and manganese measured in a depth direction from the surface of the base steel sheet has a maximum point in the depth direction from the surface, and an absolute value of a difference between a depth at which the maximum point of the concentration profile of oxygen is formed and a depth at which the maximum point of the concentration profile of one of silicon and manganese is formed is 0.5 ?m or less.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: Provided are a method and device for controlling a wind speed parameter of a wind-based power generation facility which include a memory; and a processor connected to the memory, wherein the processor is configured to: receive a first wind speed corresponding to an average wind speed per a preset time interval from a first real-world wind-based power generation facility installed in a real world, and receive therefrom a first power generation amount as generated per the preset time interval; generate a first dataset representing a power generation amount based on a change in a wind speed, based on the first wind speed and the first power generation amount; calculate a first power coefficient related to the first power generation amount based on each first wind speed, based on the first data set.

Abstract: A method and a device for shard communication in a wireless LAN are disclosed. A method of a first STA comprises the steps of: receiving a first frame for allocation of a shared communication period from an AP; identifying the shared communication period on the basis of one or more fields included in the first frame; and performing shared communication with a second STA in the shared communication period, wherein the shared communication period is configured within a TXOP configured between the AP and a third STA.

Abstract: A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

Abstract: One or more embodiments provide a light-emitting display device including a substrate, a first transistor including a lower electrode above the substrate, a first semiconductor overlapping the lower electrode, and a first gate electrode overlapping the first semiconductor, a light-emitting diode electrically connected to the first transistor, a storage capacitor including a first storage electrode electrically connected to the lower electrode, and a second storage electrode overlapping the first storage electrode, a shielding electrode at a same layer as the lower electrode or as the first semiconductor, a data line overlapping the shielding electrode, and configured to transmit a data voltage, and an auxiliary electrode between the shielding electrode and the data line, overlapping the shielding electrode, and adjacent to the first gate electrode.

Abstract: A method of manufacturing a semiconductor device that includes providing a substrate having a pattern formed thereon. A scanning electron microscope (SEM) image is generated that includes a boundary image showing an edge of the pattern. A blended image is generated by performing at least one blending operation on the SEM image and a background image aligned with the boundary image. Contour data is generated by binarizing the blended image on a basis of a threshold value. The threshold value is determined by a critical dimension of the pattern.

Abstract: Disclosed herein are a dynamic memory management apparatus and method and a computer-readable storage medium for the same. The dynamic memory management method includes defining a shadow area mapped to a memory area, setting a coloring value in the shadow area, and permitting or denying access to the memory area based on the coloring value when accessing the memory area.

Abstract: A coil component includes a body; a support substrate disposed in the body; a coil portion including a first coil pattern, a first lead-out pattern, and a second lead-out pattern; a first slit portion defined at a corner portion between the first end surface and the first surface, and a second slit portion defined at a corner portion between the second end surface and the first surface, the first and second slit portions exposing the first and second lead-out patterns; a first external electrode and a second external electrode spaced apart from each other on the first surface, and respectively extending onto the first and second slit portions to be connected to the first and second lead-out patterns; and a surface insulating layer disposed on the first and second slit portions to cover a portion of the first and second external electrodes and extending onto the first surface.

Abstract: A pixel includes a first transistor connected between a first power line and a first node, and including a gate electrode connected to a second node, a second transistor connected between a data line and the second node, and including a gate electrode connected to a scan line, a third transistor connected between a first sensing line and the first node, and including a gate electrode connected to a first control line, a fourth transistor connected between a second sensing line and a third node, and including gate electrode connected to a second control line, a first sub light emitting unit including light emitting elements connected in parallel in a forward direction between the first node and the third node, and a second sub light emitting unit including light emitting elements connected in parallel in the forward direction between the third node and a second power line.

Abstract: The present invention relates to a zinc plated steel sheet having excellent surface quality and spot weldability, and a manufacturing method therefore. A zinc plated steel sheet according to one aspect of the present invention comprises a base steel sheet and a zinc-based plating layer formed on the surface of the base steel sheet, wherein the GDOES profile of oxygen, which is measured in the depth direction from the surface of the base steel sheet, has a form in which a local minimum point and a local maximum point alternately appear in the depth direction from the surface, and the difference (a local maximum value?a local minimum value) between the oxygen concentration (a local minimum value) at the local minimum point and the oxygen concentration (a local maximum value) at the local maximum point can be 0.1 wt % or more.

Abstract: A method and apparatus for estimating a physical property parameter of a target fabric include receiving a two-dimensional (2D) image capturing a drape shape of the target fabric and basic information of the target fabric, estimating the physical property parameter of the target fabric including at least one of a stretching parameter of the target fabric and a bending parameter of the target fabric by applying the 2D image and the basic information of the target fabric to a neural network model, and outputting the physical property parameter of the target fabric.

Abstract: A home ice maker is proposed. According to the home ice maker, without rocking an ice making tray, ice-making water is allowed to sufficiently fluctuate by the rotation of the fluctuation part, thereby easily forming transparent ice without increasing the size of the ice making tray. The fluctuation part and the ice making tray are formed coaxially, and when rotating the fluctuation part so as to remove ice, the fluctuation part is rotated relative to the central axis of the ice making tray, thereby realizing a compact configuration of the ice maker without requiring additional space for the ice removal.

Abstract: A semiconductor package including first and second chip stacks each including semiconductor chips having an offset stack structure, the second chip stack horizontally spaced apart from the first chip stack, a first buffer chip on the substrate and at a side of the first chip stack, a second buffer chip on the substrate and at a side of the second chip stack, a connection substrate on the first and second chip stacks, a first mold layer covering the substrate, the first chip stack, and the second stack and exposing a top surface of the connection substrate, third and fourth chip stacks each including semiconductor chips having an offset stack structure on the first mold layer and, the fourth chip stack horizontally spaced apart from the third chip stack, and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack may be provided.