Abstract: A semiconductor manufacturing apparatus may include: a first chamber including a first internal space; an ion generator configured to generate ions within the first internal space; a second chamber including a second internal space, the second internal space communicatively connected to the first internal space; a beam generator between the first internal space and the second internal space and configured to convert the ions into ion beams; a chuck within the second chamber; and a reflector within the second chamber, the reflector including a reflective surface that is curved, and the reflector configured to reflect the ion beams toward the chuck.

Abstract: A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; first source/drain regions respectively disposed on opposite sides of the first gate structure; second source/drain regions respectively disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, including a first insulating material; and a gate capping layer disposed on the first and second gate structures.

Abstract: A semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps; first and second semiconductor devices on the interposer and spaced apart from each other, mounted on the interposer via second conductive bumps and having concavo-convex patterns respectively formed in upper surfaces thereof; and a sealing member on the interposer covering the first and second semiconductor devices and exposing the concavo-convex patterns. The concavo-convex pattern of the first semiconductor device includes a plurality of first pillar structures provided in the upper surface of a first region of the first semiconductor device and having a first width, and a plurality of second pillar structures provided in the upper surface of a second region of the first semiconductor device and having a second width greater than the first width.

Abstract: A semiconductor memory device includes: a substrate having first and second channel structures extending in a first direction arranged spaced apart in a second direction; a first gate structure disposed on the first channel structure; a second gate structure disposed on the second channel structure; first source/drain regions disposed on opposite sides of the first gate structure; second source/drain regions disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the gate structures to directly contact the gate structures and having an upper surface disposed at a level lower than an upper surface of the gate structures along a third direction; and a gate capping layer disposed on the gate structures and having an extension portion disposed between the gate structures such that the extension portion directly contacts the gate structures, the gate capping layer being connected to the gate separation pattern.

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a gate electrode including a first gate electrode on the first active pattern and a second gate electrode on the second active pattern, a gate cutting pattern between the first and second gate electrodes, gate spacers on opposing side surfaces of the gate electrode, and a gate capping pattern on top surfaces of the gate electrode, the gate cutting pattern, and the gate spacers and extending in the first direction. The gate cutting pattern includes a first and second side surfaces, which are opposite to each other in a second direction crossing the first direction. The first and side surfaces are in contact with respective ones of the gate spacers, and the top surface of the gate cutting pattern is closer to the substrate than the top surfaces of the pair of gate spacers.

Abstract: Provided is a plasma processing device. The plasma processing device includes a dual chamber system including a first chamber and a second chamber fluidly connected to the first chamber through an opening, a first gas injector configured to supply a first gas to the first chamber, a grid positioned at the opening between the first chamber and the second chamber, a second chamber shutter, a second gas injector configured to inject a second gas into the second chamber, and a wafer stage positioned inside the second chamber and having a wafer support surface, wherein the second chamber shutter is configured to transition between an open state in which the grid is fluidly connected to the second chamber and a closed state in which the grid is not fluidly connected to the second chamber.

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes: a substrate extending in first and second directions intersecting each other; a non-conductive material layer on the substrate; and a semiconductor chip on the non-conductive material layer, wherein the non-conductive material layer includes a plurality of first recess areas, wherein each of the plurality of first recess areas extends in the first direction and inwardly of a side surface of the semiconductor chip, wherein the plurality of first recess areas are spaced apart from each other in the second direction, wherein at least one of the plurality of first recess areas defines a void.

Abstract: The present invention provides a carbon fiber, which has excellent tensile strength by having fewer internal defects while being a thick fiber having a single-fiber diameter of 6.0 ?m or greater, and can provide the effects of reducing costs while increasing production amount to enhance the yieldability of the carbon fiber.

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having a first front surface and a first rear surface, first front pads, a first interlayer insulating layer between the first front pads and the first substrate, and a first interconnection structure in the first interlayer insulating layer and connected to the first front pads, and a front cover layer on the first interlayer insulating layer and including openings respectively exposing at least a portion of each of the first front pads, where a thermal conductivity of the front cover layer is smaller than a thermal conductivity of the first interlayer insulating layer and a thermal conductivity of the first substrate.

Abstract: A magnetic memory device includes a substrate, an interlayer insulating layer on the substrate, a data storage structure on the interlayer insulating layer, and a plurality of metal oxides on at least one side surface of the data storage structure, where the data storage structure includes a lower electrode, a magnetic tunnel junction pattern, and an upper electrode sequentially stacked on the interlayer insulating layer, and at least one metal oxide of the plurality of metal oxides contacts a side surface of the upper electrode.

Abstract: A video output device includes: a display unit configured to output a video signal received from an outside; an input unit into which user's selection information on an output mode of the display unit is input from a user; and a communication unit configured to transmit pixel information of the display unit corresponding to the selection information input through the input unit to a video signal transmission device. The video output device allows a user to freely adjust the size of an output image on the display unit by changing a video signal received from an outside according to the user's selection.

Abstract: A semiconductor device is provided.

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral region, a plurality of data storage patterns on the cell region and each including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked, and a magnetic shield layer at the cell region and between the data storage patterns. The magnetic shield layer has a top surface that is recessed toward the substrate between the data storage patterns.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A semiconductor package including a lower structure, a lower conductive pad disposed on an upper surface of the lower structure, a lower connection pad disposed on and connected to an upper surface of the lower conductive pad, an upper connection pad disposed on and spaced apart from an upper surface of the lower connection pad, an upper conductive pad disposed on and connected to an upper surface of the upper connection pad, an upper structure disposed on an upper surface of the upper conductive pad, and an intermetallic compound layer disposed between and in contact with at least a portion of the upper surface of the lower connection pad and a lower surface of the upper connection pad, where the intermetallic compound layer includes an intermetallic compound including the first metal, the second metal, and a third metal different from each of the first metal and the second metal.

Abstract: A semiconductor device includes: a substrate; an active pattern and a field insulating layer surrounding a sidewall of the active pattern on the substrate; first and second gate electrodes on the active pattern and extending in a direction different from that of the active pattern; an interlayer insulating layer surrounding a sidewall of each of the first and second gate electrodes; a gate spacer on opposing sidewalls of each of the first and second gate electrodes that includes a first sidewall and a second sidewall opposite the first sidewall in the first horizontal direction, each of which contacts the interlayer insulating layer; and a first gate cut dividing the second gate electrode into two portions, wherein the first gate cut includes a same material as the gate spacer; and wherein a first width of the first gate cut is smaller than a second width of the gate spacer.

Abstract: The present invention relates to a polyester tire cord made of polyester yarn and having a 5% LASE of 1.2 g/d or more as measured according to ASTM D885 at 80° C., a 5% LASE of 1.0 g/d or more as measured according to ASTM D885 at 120° C., and a toughness retention rate of 65% or more at 80° C. and 120° C. The tire cord of the present invention has a modulus comparable to that of rayon even in a high-temperature environment at 120° C. or higher, and has excellent dimensional stability and heat resistance, and thus it can be advantageously applied to a high-performance tire.

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.