Patents by Inventor Cheol-kyu Lee
Cheol-kyu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12260656Abstract: According to an embodiment of the present disclosure, there may be provided an operation method of a server for estimating the size of damage in disaster affected areas. In this instance, the operation method of the server may include acquiring at least one first disaster image, deriving an affected area from each of the at least one first disaster image, acquiring affected area related information through labeling based on the derived affected area, and training a first learning model using the at least one first disaster image and the affected area related information.Type: GrantFiled: May 4, 2022Date of Patent: March 25, 2025Assignee: NATIONAL DISASTER MANAGEMENT RESEARCH INSTITUTEInventors: Seong Sam Kim, Dong Yoon Shin, Cheol Kyu Lee
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Publication number: 20250044463Abstract: The present disclosure provides a location information acquisition method of a computing device, including the steps of: acquiring first location information at which an electro-optical topographic surveying device is located in response to a received satellite Global Navigation Satellite System (GNSS) signal; acquiring photography information for positioning of a target object photographed by a drone while the drone is flying in a GNSS shadow area from the drone equipped with a survey prism that reflects light waves from the surveying device; calculating absolute coordinates of the target object corresponding to the surveying device based on reflective metering of the survey prism and the photography information for positioning; and calculating GNSS based second location information as location information of the target object using the absolute coordinates and the first location information.Type: ApplicationFiled: July 17, 2024Publication date: February 6, 2025Inventors: Seong Sam Kim, Jae-Wook Seok, Yong-Han Jung, Eon-taek Lim, Seul Koo, Cheol-Kyu Lee
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Patent number: 12154311Abstract: An operation method of a server for identifying disaster affected areas. The operation method of the server may include acquiring at least one first disaster image; deriving an affected area from each of the at least one first disaster image and acquiring affected area related information through labeling based on the derived affected area; and training a first learning model using the at least one first disaster image and the affected area related information.Type: GrantFiled: May 4, 2022Date of Patent: November 26, 2024Assignee: NATIONAL DISASTER MANAGEMENT RESEARCH INSTITUTEInventors: Seong Sam Kim, Dong Yoon Shin, Cheol Kyu Lee
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Patent number: 12087148Abstract: A device for establishing a communication network and collecting situation information at a site of a collapse disaster is disclosed. The device includes a ground drone 10 deployed at the site of the collapse disaster, the ground drone 10 having a communication device 80 mounted thereon, a flying drone 32 mounted on and carried by the ground drone 10 to fly and photograph the site of the collapse disaster, a camera device 40 mounted on the ground drone 10 to photograph surroundings of the ground drone 10, a storage 50 installed on the ground drone 10, and a plurality of repeater modules 60 connected by the wireless communication network to relay wireless communications between the ground drone 10, the flying drone 32, and a command and control center 100, wherein the storage 50 accommodates the repeater modules 60, and throws the repeater modules 60 in response to an operation signal.Type: GrantFiled: June 21, 2023Date of Patent: September 10, 2024Assignee: Republic of Korea (National Disaster Management Research Institute)Inventors: Si Beum Cho, Kyung Su Lee, Jae Jeong Kim, Cheol Kyu Lee, Tae Wook Lee
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Patent number: 12081911Abstract: A buried person search device using a detachable module is disclosed. The device includes a ground drone 10 deployed at a site of a collapse disaster, the ground drone 10 having a communication device 80 and a first beacon, a camera device 40 mounted on the ground drone 10 to photograph surroundings of the ground drone 10, a storage 50 installed on the ground drone 10, a plurality of repeater modules 60 connected by a wireless communication network to relay wireless communications between the ground drone 10, a flying drone 32, and a command and control center 100, each of the repeater modules 60 having a second beacon, and a sensing device 70 installed on the ground drone 10 or the repeater modules 60 to collect a sound, wherein the storage 50 accommodates the repeater modules 60, and throws the repeater modules 60 in response to an operation signal.Type: GrantFiled: June 21, 2023Date of Patent: September 3, 2024Assignee: Republic of Korea (National Disaster Management Research Institute)Inventors: Si Beum Cho, Kyung Su Lee, Jae Jeong Kim, Cheol Kyu Lee, Tae Wook Lee
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Publication number: 20240161597Abstract: A device for establishing a communication network and collecting situation information at a site of a collapse disaster is disclosed. The device includes a ground drone 10 deployed at the site of the collapse disaster, the ground drone 10 having a communication device 80 mounted thereon, a flying drone 32 mounted on and carried by the ground drone 10 to fly and photograph the site of the collapse disaster, a camera device 40 mounted on the ground drone 10 to photograph surroundings of the ground drone 10, a storage 50 installed on the ground drone 10, and a plurality of repeater modules 60 connected by the wireless communication network to relay wireless communications between the ground drone 10, the flying drone 32, and a command and control center 100, wherein the storage 50 accommodates the repeater modules 60, and throws the repeater modules 60 in response to an operation signal.Type: ApplicationFiled: June 21, 2023Publication date: May 16, 2024Inventors: Si Beum CHO, Kyung Su LEE, Jae Jeong KIM, Cheol Kyu LEE, Tae Wook LEE
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Publication number: 20240163401Abstract: A buried person search device using a detachable module is disclosed. The device includes a ground drone 10 deployed at a site of a collapse disaster, the ground drone 10 having a communication device 80 and a first beacon, a camera device 40 mounted on the ground drone 10 to photograph surroundings of the ground drone 10, a storage 50 installed on the ground drone 10, a plurality of repeater modules 60 connected by a wireless communication network to relay wireless communications between the ground drone 10, a flying drone 32, and a command and control center 100, each of the repeater modules 60 having a second beacon, and a sensing device 70 installed on the ground drone 10 or the repeater modules 60 to collect a sound, wherein the storage 50 accommodates the repeater modules 60, and throws the repeater modules 60 in response to an operation signal.Type: ApplicationFiled: June 21, 2023Publication date: May 16, 2024Inventors: Si Beum CHO, Kyung Su LEE, Jae Jeong KIM, Cheol Kyu LEE, Tae Wook LEE
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Publication number: 20220358746Abstract: According to an embodiment of the present disclosure, there may be provided an operation method of a server for identifying disaster affected areas. In this instance, the operation method of the server may include acquiring at least one first disaster image; deriving an affected area from each of the at least one first disaster image, and acquiring affected area related information through labeling based on the derived affected area; and training a first learning model using the at least one first disaster image and the affected area related information.Type: ApplicationFiled: May 4, 2022Publication date: November 10, 2022Applicant: NATIONAL DISASTER MANAGEMENT RESEARCH INSTITUTEInventors: Seong Sam KIM, Dong Yoon SHIN, Cheol Kyu LEE
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Publication number: 20220358774Abstract: According to an embodiment of the present disclosure, there may be provided an operation method of a server for estimating the size of damage in disaster affected areas. In this instance, the operation method of the server may include acquiring at least one first disaster image, deriving an affected area from each of the at least one first disaster image, acquiring affected area related information through labeling based on the derived affected area, and training a first learning model using the at least one first disaster image and the affected area related information.Type: ApplicationFiled: May 4, 2022Publication date: November 10, 2022Applicant: NATIONAL DISASTER MANAGEMENT RESEARCH INSTITUTEInventors: Seong Sam KIM, Dong Yoon SHIN, Cheol Kyu LEE
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Patent number: 7879726Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.Type: GrantFiled: August 7, 2008Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Sik Park, Jun-Ho Yoon, Cheol-Kyu Lee, Joon-Soo Park
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Patent number: 7879703Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.Type: GrantFiled: January 20, 2009Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Ho Jung, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Joon-Seok Moon, Cheol-Kyu Lee, Sung-Il Cho
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Patent number: 7763544Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched.Type: GrantFiled: July 1, 2009Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Keun-Hee Bai, Kyeong-Koo Chi, Chang-Jin Kang, Cheol-Kyu Lee
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Patent number: 7728375Abstract: Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.Type: GrantFiled: July 21, 2008Date of Patent: June 1, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Sub Shin, Cheol-Kyu Lee, Sung-il Cho, Young-Kyu Cho
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Publication number: 20090263970Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched.Type: ApplicationFiled: July 1, 2009Publication date: October 22, 2009Inventors: Keun-Hee BAI, Kyeong-Koo CHI, Chang-Jin KANG, Cheol-Kyu LEE
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Patent number: 7566659Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched.Type: GrantFiled: June 21, 2005Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Keun-Hee Bai, Kyeong-Koo Chi, Chang-Jin Kang, Cheol-Kyu Lee
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Publication number: 20090186471Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.Type: ApplicationFiled: January 20, 2009Publication date: July 23, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Kyoung-Ho Jung, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Joon-Seok Moon, Cheol-Kyu Lee, Sung-Il Cho
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Publication number: 20090042396Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.Type: ApplicationFiled: August 7, 2008Publication date: February 12, 2009Inventors: Heung-Sik Park, Jun-Ho Yoon, Cheol-Kyu Lee, Joon-Soo Park
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Publication number: 20090026515Abstract: Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.Type: ApplicationFiled: July 21, 2008Publication date: January 29, 2009Inventors: Kyoung-Sub Shin, Cheol-Kyu Lee, Sung-il Cho, Young-Kyu Cho
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Patent number: 7402488Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.Type: GrantFiled: June 23, 2005Date of Patent: July 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-il Cho, Kyeong-koo Chi, Seung-pil Chung, Chang-jin Kang, Cheol-kyu Lee
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Patent number: 7329574Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.Type: GrantFiled: June 16, 2005Date of Patent: February 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Cho, Jong-Kyu Kim, Byeong-Yun Nam, Kyeong-Koo Chi, Cheol-Kyu Lee