Abstract: The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are improved.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: A weak point detecting method of the present invention designs a target layout, and compensates an optical proximity effect for the target layout, thereafter, verifies the target layout in which the optical proximity effect is compensated by using an NILS of the target layout, thereby, enabling to reduce the time and cost in detecting a weak point for a full chip regardless of the size and form of a pattern.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: Provided is a method for optical proximity correction for use in manufacturing highly resolved semiconductor chips. The method includes setting a target layout; setting a peculiar area; sorting the peculiar area from the target layout; generating a marking layer; resetting a critical dimension (CD) of a peculiar pattern; compensating an optical proximity effect; and manufacturing a mask. The method provides an improved way of improving more accurately CD uniformity by performing optical proximity correction with respect to a pattern to which a bias rule is difficult to apply due to an absence of an adjacent pattern.

Abstract: A method for processing optical proximity correction includes preparing a chemical mechanical polishing (CMP) map; extracting calibration data depending on a focus degree with the CMP map; and correcting optical proximity with the calibration data.

Abstract: Provided is a method for optical proximity correction for use in manufacturing highly resolved semiconductor chips. The method includes setting a target layout; setting a peculiar area; sorting the peculiar area from the target layout; generating a marking layer; resetting a critical dimension (CD) of a peculiar pattern; compensating an optical proximity effect; and manufacturing a mask. The method provides an improved way of improving more accurately CD uniformity by performing optical proximity correction with respect to a pattern to which a bias rule is difficult to apply due to an absence of an adjacent pattern.

Abstract: A method of manufacturing a semiconductor device, particularly a vertical transistor, including forming a contact hole and forming a pillar using an epitaxial growth process.

Abstract: A weak point detecting method of the present invention designs a target layout, and compensates an optical proximity effect for the target layout, thereafter, verifies the target layout in which the optical proximity effect is compensated by using an NILS of the target layout, thereby, enabling to reduce the time and cost in detecting a weak point for a full chip regardless of the size and form of a pattern.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: A method for processing optical proximity correction includes preparing a chemical mechanical polishing (CMP) map; extracting calibration data depending on a focus degree with the CMP map; and correcting optical proximity with the calibration data.

Abstract: A method of manufacturing a semiconductor device, particularly a vertical transistor, including forming a contact hole and forming a pillar using an epitaxial growth process.

Abstract: The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are improved.

Abstract: The present invention relates to a stencil mask for non-optical lithography and a method for fabricating such a mask. The disclosed stencil mask includes a frame for supporting the whole structure; a membrane disposed on the frame for equalizing stresses resulting from the electron beam; and a scattering layer pattern disposed on the membrane for scattering the electron beam. The scattering layer pattern includes regions of varying thickness and/or scattering performance that permit the exposure to be adjusted for areas having greater or lesser pattern density. These adjustments can reduce defects resulting from proximity effects, improve the uniformity of critical features, and improve the yield and reliability of the resulting devices.

Abstract: Disclosed is a novel method for fabricating a stencil mask comprising the formation of an absorber pattern, including an alignment key or target, on the topside of an SOI wafer having a transparent buried insulating layer. The formation of the absorber pattern is followed by the formation of an alignment window from the backside of the SOI wafer using the insulating layer as a lens. The alignment window allows the alignment between the absorber pattern and the frame pattern to be verified, using light passing through the window lens and illuminating the alignment key, before initiating the frame etch, thereby improving the quality and/or throughput of the stencil mask manufacturing process.

Abstract: The present invention relates to a stencil mask for non-optical lithography and a method for fabricating such a mask. The disclosed stencil mask includes a frame for supporting the whole structure; a membrane disposed on the frame for equalizing stresses resulting from the electron beam; and a scattering layer pattern disposed on the membrane for scattering the electron beam. The scattering layer pattern includes regions of varying thickness and/or scattering performance that permit the exposure to be adjusted for areas having greater or lesser pattern density. These adjustments can reduce defects resulting from proximity effects, improve the uniformity of critical features, and improve the yield and reliability of the resulting devices.

Abstract: Disclosed is a novel method for fabricating a stencil mask comprising the formation of an absorber pattern, including an alignment key or target, on the topside of an SOI wafer having a transparent buried insulating layer. The formation of the absorber pattern is followed by the formation of an alignment window from the backside of the SOI wafer using the insulating layer as a lens. The alignment window allows the alignment between the absorber pattern and the frame pattern to be verified, using light passing through the window lens and illuminating the alignment key, before initiating the frame etch, thereby improving the quality and/or throughput of the stencil mask manufacturing process.

Abstract: A stencil mask used as an exposure mask in a non-optical lithography process using an electron beam, X-ray or ion beam as a light source, comprising: a membrane; and a layer formed over the membrane, for scattering or absorbing electrons, wherein the layer for scattering or absorbing has a multi-layered structure in which two or more layers comprised of different materials are stacked.

Abstract: Disclosed herein is a method of fabricating a stencil mask to be used in an E-beam lithographic process. The method comprises, after forming a silicon nitride film over the entire surface of a wafer, a step of dividing the silicon nitride film into at least two sub-portions to form silicon nitride film patterns. A stress applied to the silicon nitride film is thus reduced.