Abstract: The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

Abstract: A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, a first trench penetrating the dielectric layer on the isolation layer to separate parts of the dielectric layer, a second trench formed on the isolation layer and expanded from the first trench, and a second conductive layer formed over the dielectric layer to fill the first and second trenches.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Abstract: The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

Abstract: A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

Abstract: A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench.

Abstract: A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.

Abstract: The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

Abstract: A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.

Abstract: A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

Abstract: Disclosed herein is a method of forming a metal line of a semiconductor device. According to the method, a contact hole is formed in a second insulating layer over a semiconductor substrate. A first barrier metal layer, including a TiN layer, is formed on a surface of the second insulating layer. The first barrier metal layer is formed such that the TiN layer is formed thinner at a bottom of the contact hole than on sidewalls and a top surface of the second insulating layer. A first metal layer is formed on the first barrier metal layer, including on the contact hole. Thermal treatment is carried to gap-fill the contact hole as the first metal layer is reflown and smooth. A second metal layer is formed on the first metal layer. The second metal layer to form an upper metal line.

Abstract: The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

Abstract: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

Abstract: A method of manufacturing a non-volatile memory device includes forming a trench using the shallow trench isolation (STI) method; forming a first insulating layer on a semiconductor device including the trench; forming a conductive layer on the semiconductor device including the trench; etching the conductive layer to form a conductive layer for a floating gate on an active area and to form a recessed gap-fill conductive layer on an isolation layer; forming a second insulating layer and a third insulating layer on the semiconductor substrate including the gap fill conductive layer and the conductive layer for the floating gate; and etching a portion of the second insulating layer and the third insulating layer to form an isolation structure consisting of the gap fill conductive layer, the second insulating layer and the third insulating layer on the isolation area.

Abstract: A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

Abstract: According to a method of forming a metal wiring of a semiconductor device, a contact plug is formed at height lower than the contact hole, which is formed on an interlayer insulation layer, and then a metal wiring is formed over the contact plug and interlayer insulation layer to completely fill inside of the contact hole, decreasing process difficulty, ensuring reproducibility, and improving electrical property.

Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.