Abstract: A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

Abstract: A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.