Abstract: A multiple chip memory system capable of providing state information relating to each chip embedded therein. The multiple chip memory system includes a first chip enabled by a first chip selection signal, and informing of a self state by a first ready/busy signal; and a second chip enabled by a second chip selection signal, and informing of a self state by a second ready/busy signal.

Abstract: A multiple chip memory system capable of providing state information relating to each chip embedded therein. The multiple chip memory system includes a first chip enabled by a first chip selection signal, and informing of a self state by a first ready/busy signal; and a second chip enabled by a second chip selection signal, and informing of a self state by a second ready/busy signal.

Abstract: Disclosed herein is an integrated circuit memory device which includes a memory cell arranged at an intersection of a word line and a bit line and a bit line precharge circuit for providing the bit line with a predetermined current during respective bit line precharge and sensing periods of time of a data reading operation in response to a bit line precharge signal. The integrated circuit memory device further includes a bit line pass transistor which has a gate and connected between the bit line precharge circuit and the bit line and which transfers the current from the bit line precharge circuit onto the bit line. Furthermore, the device includes a bias voltage supplying circuit which supplies the gate of the bit line pass transistor with a bias voltage during the data reading operation.

Abstract: A semiconductor read-only memory includes a main memory cell array having a plurality of first and second bit lines arranged in a hierarchical configuration. A dummy cell array generates a reference potential during a read-out operation. A decoder circuit generates a first, second, third and fourth selection signals from address signals, and a sense amplifier circuit detects data stored in a memory cell of the main memory cell array. A switching circuit connects the dummy cell to the sense amplifier circuit through the second bit line. The read-only memory according to the invention has an advantage that it is possible to accomplish an efficient read-out operation without additional dummy bit lines in an area of the memory cell array.

Abstract: A NOR-type read only memory with improved read-out performance includes a memory cell array having a plurality of memory cell blocks, each memory block including a plurality of bit lines, a column decoder for generating a plurality of decoding signals in response to a plurality of address signals, a first bias/ground selection control circuit for generating a plurality of first bias/ground selection signals determining bias conditions for a first group of the plurality of bit lines, a first bias/ground selection circuit for establishing bias conditions of the first group of the plurality of bit lines in response to the first bias/ground selection signals generated from the first bias/ground selection control circuit, a second bias/ground selection control circuit for generating a plurality of second bias/ground selection signals determining bias conditions of a second group of the plurality of bit lines, and a second bias/ground selection circuit for establishing bias conditions of the second group of the plu

Abstract: A memory having a read function for generating a plurality of data bits on a single output pin includes a control circuit, a sense amplifier circuit, and a decoder. The control circuit generates a decoder control pulse responding to the control pulse generated from an address transition detector receiving a first address. The sense amplifier circuit senses data bits from a memory array of the memory and is coupled to the output pin through a data output buffer. The decoder receives a second address and provides decoding signals to the sense amplifier circuitry in response to the control pulse generated from the control circuit. The read-out operation according to the invention is performed sufficiently and stably even when a propagation skew occurs between the first address and the second address.

Abstract: Disclosed is a NOR type mask ROM device with a hierarchical bit line architecture in which metal oxide semiconductor FETs constituting memory cells are connected in parallel to one another.

Abstract: A semiconductor integrated circuit having an address transition detector includes a power detecting circuit connected to a source terminal for detecting a voltage level of the source terminal, a pulse generating circuit for receiving an address signal and generating a pulse when the address signal is changed, and a summator for combining outputs of the power detecting circuit and the pulse generating circuit and generating a given pulse when the outputs vary.

Abstract: A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

Abstract: A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.