Patents by Inventor Cheolin Jang

Cheolin Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100596
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: September 24, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunki Lee, Duck-Nam Kim, Keunhee Bai, Sae Il Son, Kwang-Ho You, Cheolin Jang
  • Publication number: 20230042905
    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.
    Type: Application
    Filed: March 25, 2022
    Publication date: February 9, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yongchul JEONG, Sangjin KIM, Yigwon KIM, Kyeongbeom PARK, Suhyun BARK, Sangshin JANG, Jinhee JANG, Cheolin JANG, Tae Min CHOI
  • Publication number: 20220293426
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.
    Type: Application
    Filed: December 16, 2021
    Publication date: September 15, 2022
    Inventors: Hyunki Lee, Duck-Nam Kim, Keunhee Bai, Sae IL Son, Kwang-Ho You, Cheolin Jang