Abstract: An emulation system comprises a first computing device having a processor configured to generate a synchronization clock signal on receiving a data transfer request. The first computing device further comprises a first non-transitory machine-readable memory buffer storing machine readable binary data. The emulation system further comprises an emulator controller configured to receive the synchronization clock signal from the first computing device. The emulation system further comprises a memory port controller configured to initiate transfer of the machine readable binary data from the first non-transitory machine-readable memory buffer to a non-transitory machine-readable hardware memory, in response to receiving the synchronization clock signal from the emulator controller, during a latency period of the synchronization clock signal.

Abstract: Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base functions that include two-input threshold OR functions and two-input threshold AND functions with hysteresis, and complex base functions generated during the decomposing; partitioning the network of base functions into at least one subject graph, each portion of the at least one subject graph having a function; determining matches between the at least one subject graph and one or more pattern graphs; and selecting at least one of the one or more pattern graphs to be used in the bound network for the function of each of different portions of the at least one subject graph.

Abstract: Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex.

Abstract: Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex.

Abstract: Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base functions that include two-input threshold OR functions and two-input threshold AND functions with hysteresis, and complex base functions generated during the decomposing; partitioning the network of base functions into at least one subject graph, each portion of the at least one subject graph having a function; determining matches between the at least one subject graph and one or more pattern graphs; and selecting at least one of the one or more pattern graphs to be used in the bound network for the function of each of different portions of the at least one subject graph.