Patents by Inventor Cheon An Lee
Cheon An Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250240968Abstract: A semiconductor device includes a semiconductor substrate that includes a first transistor region and a second transistor region, a plurality of transistors that include a first transistor located in the first transistor region and a second transistor located in the second transistor region and that has a greater operating voltage than the first transistor, and a first metal layer disposed on the first transistor and the second transistor. The first metal layer overlaps the second transistor and does not overlap a neighboring second transistor, and the first metal layer overlaps the first transistor and includes a wire that overlaps a neighboring first transistor.Type: ApplicationFiled: December 11, 2024Publication date: July 24, 2025Inventors: SANGEUN LEE, CHANHO LEE, SUKKANG SUNG, CHEON AN LEE
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Publication number: 20240055469Abstract: The present disclosure relates to a semiconductor device, and more particularly, relates to a non-volatile memory device having a three-dimensional structure. The non-volatile memory device according to an embodiment of the present disclosure includes a first chip having a peripheral circuit therein and a second chip that is stacked on the first chip and that includes memory blocks. The second chip includes a common source line that has a plate shape and extends in first and second directions, first and second dummy common source lines disposed at a same height level as the common source line, an upper insulating layer that covers the common source line and the first and second dummy common source lines, and first and second dummy contact plugs extending in a third direction and that are electrically connected to the first and second dummy common source lines, respectively, and used as electrodes of a vertical capacitor.Type: ApplicationFiled: April 24, 2023Publication date: February 15, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Chang-Bum KIM, Cheon An LEE, Sukkang SUNG
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Patent number: 10395727Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.Type: GrantFiled: March 16, 2018Date of Patent: August 27, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Ho Yu, Dae-Seok Byeon, Jin-Bae Bang, Cheon-An Lee
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Publication number: 20190096479Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.Type: ApplicationFiled: March 16, 2018Publication date: March 28, 2019Inventors: CHUNG-HO YU, DAE-SEOK BYEON, JIN-BAE BANG, CHEON-AN LEE
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Patent number: 9805807Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.Type: GrantFiled: January 21, 2016Date of Patent: October 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon An Lee, Mu-Hui Park, Jiho Cho, Ji-Young Lee, Yoon-Hee Choi
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Publication number: 20160260489Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.Type: ApplicationFiled: January 21, 2016Publication date: September 8, 2016Inventors: CHEON AN LEE, MU-HUI PARK, JIHO CHO, JI-YOUNG LEE, YOON-HEE CHOI
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Patent number: 9224462Abstract: A resistive memory device that simultaneously erases memory cells connected to selected word line(s) included in an erase unit. The erase unit includes fewer word lines than are included in a memory block of the resistive memory device. However, erase verification may nonetheless be performed on a block basis.Type: GrantFiled: January 3, 2013Date of Patent: December 29, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: DongHun Kwak, Cheon-An Lee
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Patent number: 9190143Abstract: A method of operating a variable resistance memory device comprises determining a level of an access voltage based on a number of rows or columns of a cell array, and supplying the access voltage having the determined level to the cell array.Type: GrantFiled: December 4, 2012Date of Patent: November 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon An Lee, Donghun Kwak, Ingyu Baek
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Patent number: 9093157Abstract: A three-dimensional nonvolatile memory device comprises a plurality of cell strings arranged perpendicular to a substrate. The nonvolatile memory device is programmed by identifying a selected word line and a plurality of unselected word lines connected to at least one of the cell stings, and sequentially applying a negative voltage and a pass voltage to the selected and unselected word lines, and then applying a program voltage to the selected word line while continuing to apply the pass voltage to the unselected word lines.Type: GrantFiled: November 7, 2012Date of Patent: July 28, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Donghun Kwak, Suna Kim, Cheon An Lee, Ho-Chul Lee
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Patent number: 8929124Abstract: A resistive memory device includes a resistive memory cell, and a read/program circuit configured to program the resistive memory cell from a first state to a second state. The read/program circuit reads a resistance in the first state of the resistive memory cell and adjusts a compliance current supplied to the resistive memory cell according to the read resistance during the program operation.Type: GrantFiled: February 13, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dae Han Kim, Cheon An Lee
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Patent number: 8917535Abstract: A variable resistance memory device comprises a variable resistance memory cells and a read/write circuit configured to provide a program voltage to the variable resistance memory cell, and further configured to adjust a compliance current flowing through the variable resistance memory cell in successive loops of a program operation.Type: GrantFiled: October 10, 2012Date of Patent: December 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon An Lee, Donghun Kwak
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Patent number: 8755242Abstract: A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first delay circuit configured to output the second clock signal by delaying the first clock signal by a first delay time. The first delay circuit is configured to adjust the first delay time according to a period of the first clock signal.Type: GrantFiled: January 20, 2012Date of Patent: June 17, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon An Lee, Doogon Kim
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Patent number: 8729615Abstract: A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.Type: GrantFiled: September 29, 2011Date of Patent: May 20, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Chang Hyun Lee, Young-Woo Park, Kye-Hyun Kyung, Cheon-An Lee, Sung-il Chang, Chul Bum Kim
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Publication number: 20130242675Abstract: A three-dimensional nonvolatile memory device comprises a plurality of cell strings arranged perpendicular to a substrate. The nonvolatile memory device is programmed by identifying a selected word line and a plurality of unselected word lines connected to at least one of the cell stings, and sequentially applying a negative voltage and a pass voltage to the selected and unselected word lines, and then applying a program voltage to the selected word line while continuing to apply the pass voltage to the unselected word lines.Type: ApplicationFiled: November 7, 2012Publication date: September 19, 2013Inventors: DONGHUN KWAK, SUNA KIM, CHEON AN LEE, HO-CHUL LEE
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Publication number: 20130235648Abstract: A resistive memory device comprises a resistive memory cell, and a read/program circuit configured to program the resistive memory cell from a first state to a second state. The read/program circuit reads a resistance in the first state of the resistive memory cell and adjusts a compliance current supplied to the resistive memory cell according to the read resistance during the program operation.Type: ApplicationFiled: February 13, 2013Publication date: September 12, 2013Applicant: SAMSUNG SEMICONDUCTOR CO., LTD.Inventors: DAE HAN KIM, CHEON AN LEE
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Publication number: 20130229855Abstract: Disclosed is a resistive memory device that simultaneously erases memory cells connected to selected word line(s) included in an erase unit. The erase unit includes fewer word lines than are included in a memory block of the resistive memory device. However, erase verification may nonetheless be performed on a block basis.Type: ApplicationFiled: January 3, 2013Publication date: September 5, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: DongHun Kwak, Cheon-An Lee
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Publication number: 20120236672Abstract: A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first delay circuit configured to output the second clock signal by delaying the first clock signal by a first delay time. The first delay circuit is configured to adjust the first delay time according to a period of the first clock signal.Type: ApplicationFiled: January 20, 2012Publication date: September 20, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: CHEON AN LEE, DOOGON KIM
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Patent number: 8258856Abstract: An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit.Type: GrantFiled: November 16, 2009Date of Patent: September 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon-An Lee, Seong-Jin Jang, Sang-Woong Shin
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Publication number: 20120146118Abstract: A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.Type: ApplicationFiled: September 29, 2011Publication date: June 14, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Hyun Lee, Young-Woo Park, Kye-Hyun Kyung, Cheon-An Lee, Sung-il Chang, Chul Bum Kim
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Patent number: 8194484Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.Type: GrantFiled: May 26, 2010Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon An Lee, Seong Jin Jang, Jong Pil Son, Sang Joon Hwang