Abstract: A method of processing an intelligent network service call in a service switching point (SSP) which has a DTMF processor and is connected to the originating local exchange/transit exchange to provide an intelligent network service. The SSP receives a digit from the other exchange in a R2MFC signalling mode to process a trunk signal from the other exchange upon generation of a trunk line seizure request from the other exchange. The SSP analyzes the received digit to check whether a call from the other exchange is a normal call or an intelligent network service call in which subscriber's information must be received in the middle of the service. If the call from the other exchange is the intelligent network service call, the SSP collects a calling number and a calling category from the other exchange, releases the R2MFC signalling mode and forms a speech path with the other exchange to communicate directly with a service user.

Abstract: The DRAM cell of the invention comprises a structure wherein a deep trench is formed on a silicon wafer, a stacked trench capacitor is formed around a silicon pillar associated with the trench, and a vertical transfer transistor is formed on top of the silicon pillar after the formation of the stacked trench capacitor. The transfer transistor is connected to the storage capacitor through a selectively doped n.sup.+ diffused layer, and isolation between DRAM cells is formed by the trench.

Abstract: A method for manufacturing a DRAM cell is provided having an isolation merged trench for applying to 16 megabit and 64 megabit DRAM cells, which includes the steps forming a primary dielectric for a capacitor within the interior of a trench, depositing an n.sup.+ doped polysilicon, forming a secondary dielectric and then stacking polysilicon thereon and connecting the polysilicon within an n.sup.+ diffusion layer of the bottom of the trench for forming a plate. As a result of this method all of the capacitors disposed between the n.sup.+ polysilicon storing electrode and the n.sup.+ polysilicon plate as well as the polysilicon storing electrode and the n.sup.+ diffusion layer plate are utilized as a storing capacitor.

Abstract: A DRAM cell of a stack structure having a cup-shaped polysilicon storage electrode for being applied to a 16 mega and 64 mega DRAM wherein a transfer transistor is firstly manufactured, a bit line is formed, an oxide film grid is formed between the cell and cell in the minimum design rule, and upon completing this, the polysilicon storage electrode is formed into a single or double cup shape, whereby the capacitor area is remarkably increased when compared with the conventional stacked structure DRAM cell so that the area efficiency is greatly increased and the process can be executed by such a mask number as the prior stacked structure mask layer number and the structure thereof is simple.