Abstract: A memory device includes a memory cell array including a plurality of memory blocks, a plurality of pass transistors connected between a plurality of local lines included in the plurality of memory blocks, a plurality of selection signal lines connected to two or more local lines corresponding to an identical level among the plurality of local lines, and an address decoder configured to apply a block selection voltage to a block word line connected to a gate of each of the plurality of pass transistors, and the address decoder is configured to apply a first voltage to the block word line of an unselected memory block among the plurality of memory blocks.

Abstract: An example non-volatile memory device includes a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage provided to at least one of a bit line or a common source line connected to a selected block targeted by an erase operation among the plurality of memory blocks, and a first negative bias voltage provided to a gate induced drain leakage (GIDL) line connected to the selected block, and a control logic circuit configured to control the voltage generator, wherein the erase voltage is increased and maintained constant during an erase operation on the selected block, and wherein a GIDL voltage provided to the GIDL line connected to the selected block is maintained at the first negative bias voltage and increased in response to the erase voltage increasing.

Abstract: A block selection circuit of a flash memory, includes: a first pass transistor connected to an address decoder; a second pass transistor connected in series with the first pass transistor; a first driver circuit configured to control a gate voltage of the first pass transistor based on a first enable signal; a second driver circuit to control a gate voltage of the second pass transistor based on a second enable signal; a first switch circuit to provide a first power voltage or a second power voltage to a gate of the first pass transistor through the first driver circuit based on a first switch signal; and a second switch circuit to share a plurality of memory blocks and provide the first power voltage or the second power voltage to the first switch circuit.

Abstract: A memory device for adjusting a trip level and an operating method thereof are provided. The memory device includes a cell string including memory cells, and a page buffer connected to the cell string through a bit line and configured to sense data of a selected memory cell of the memory cells through a sensing latch circuit, where the sensing latch circuit includes a sensing latch including a first inverter and a second inverter, and a trim transistor circuit electrically connected to a p-type metal oxide semiconductor (PMOS) transistor of the first inverter and configured to adjust a trip level of the sensing latch based on a trim voltage.

Abstract: An integrated circuit memory device includes a common source plate having a semiconductor material of a first conductivity type therein, and a plurality of word lines (including a dummy word line) extending on a bottom surface of the common source plate and spaced apart from each other in a first direction, which is perpendicular to the bottom surface of the common source plate. A mold insulating layer is provided, which at least partially surrounds the plurality of word lines, along with a plurality of channel structures that extend through the plurality of word lines and the mold insulating layer in the first direction. A metal layer is also provided, which extends in an upper region inside each of the plurality of channel structures, and is overlapped by the dummy word line in a direction orthogonal to the first direction.

Abstract: A block selection circuit of a flash memory, includes: a first pass transistor connected to an address decoder; a second pass transistor connected in series with the first pass transistor; a first driver circuit configured to control a gate voltage of the first pass transistor based on a first enable signal; a second driver circuit to control a gate voltage of the second pass transistor based on a second enable signal; a first switch circuit to provide a first power voltage or a second power voltage to a gate of the first pass transistor through the first driver circuit based on a first switch signal; and a second switch circuit to share a plurality of memory blocks and provide the first power voltage or the second power voltage to the first switch circuit.

Abstract: A semiconductor device includes a semiconductor substrate that includes a first transistor region and a second transistor region, a plurality of transistors that include a first transistor located in the first transistor region and a second transistor located in the second transistor region and that has a greater operating voltage than the first transistor, and a first metal layer disposed on the first transistor and the second transistor. The first metal layer overlaps the second transistor and does not overlap a neighboring second transistor, and the first metal layer overlaps the first transistor and includes a wire that overlaps a neighboring first transistor.

Abstract: The present disclosure relates to a semiconductor device, and more particularly, relates to a non-volatile memory device having a three-dimensional structure. The non-volatile memory device according to an embodiment of the present disclosure includes a first chip having a peripheral circuit therein and a second chip that is stacked on the first chip and that includes memory blocks. The second chip includes a common source line that has a plate shape and extends in first and second directions, first and second dummy common source lines disposed at a same height level as the common source line, an upper insulating layer that covers the common source line and the first and second dummy common source lines, and first and second dummy contact plugs extending in a third direction and that are electrically connected to the first and second dummy common source lines, respectively, and used as electrodes of a vertical capacitor.

Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.

Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.

Abstract: A method of operating a variable resistance memory device comprises determining a level of an access voltage based on a number of rows or columns of a cell array, and supplying the access voltage having the determined level to the cell array.

Abstract: A three-dimensional nonvolatile memory device comprises a plurality of cell strings arranged perpendicular to a substrate. The nonvolatile memory device is programmed by identifying a selected word line and a plurality of unselected word lines connected to at least one of the cell stings, and sequentially applying a negative voltage and a pass voltage to the selected and unselected word lines, and then applying a program voltage to the selected word line while continuing to apply the pass voltage to the unselected word lines.

Abstract: A resistive memory device includes a resistive memory cell, and a read/program circuit configured to program the resistive memory cell from a first state to a second state. The read/program circuit reads a resistance in the first state of the resistive memory cell and adjusts a compliance current supplied to the resistive memory cell according to the read resistance during the program operation.

Abstract: A variable resistance memory device comprises a variable resistance memory cells and a read/write circuit configured to provide a program voltage to the variable resistance memory cell, and further configured to adjust a compliance current flowing through the variable resistance memory cell in successive loops of a program operation.

Abstract: A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first delay circuit configured to output the second clock signal by delaying the first clock signal by a first delay time. The first delay circuit is configured to adjust the first delay time according to a period of the first clock signal.

Abstract: A three-dimensional nonvolatile memory device comprises a plurality of cell strings arranged perpendicular to a substrate. The nonvolatile memory device is programmed by identifying a selected word line and a plurality of unselected word lines connected to at least one of the cell stings, and sequentially applying a negative voltage and a pass voltage to the selected and unselected word lines, and then applying a program voltage to the selected word line while continuing to apply the pass voltage to the unselected word lines.

Abstract: A resistive memory device comprises a resistive memory cell, and a read/program circuit configured to program the resistive memory cell from a first state to a second state. The read/program circuit reads a resistance in the first state of the resistive memory cell and adjusts a compliance current supplied to the resistive memory cell according to the read resistance during the program operation.

Abstract: A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first delay circuit configured to output the second clock signal by delaying the first clock signal by a first delay time. The first delay circuit is configured to adjust the first delay time according to a period of the first clock signal.

Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.

Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.