Abstract: A liquefied gas storage tank includes a corner block disposed on a corner portion, wherein the corner block includes a lower block, an upper block and an upper connecting block, the upper block includes a first inner fixing unit and a second inner fixing unit respectively provided inside a first surface and a second surface, bonded and connected to a secondary barrier, and each having a structure in which a primary inner plywood, a primary corner insulating material, and a primary outer plywood are stacked, and an inner bent portion installed at a corner spatial portion between the first inner fixing unit and the second inner fixing unit, and both side surfaces of the inner bent portion that are perpendicular to the secondary barrier each have a height reduced from a total height of each of the first and second inner fixing units.

Abstract: The liquefied gas storage tank includes a primary barrier, a primary insulation wall, a secondary barrier, and a secondary insulation wall. In a state where unit elements are arranged adjacent to each other, each of the unit elements being formed by stacking the secondary insulation wall, the secondary barrier, and a fixed insulation wall which is a part of the primary insulation wall, the primary insulation wall may comprise: a connection insulation wall provided in the space between the adjacent fixed insulation walls; first slits formed between the fixed insulation walls and the connection insulation wall when the connection insulation wall is inserted and installed between the adjacent fixed insulation walls; a plurality of second slits formed in a lengthwise direction and a widthwise direction of the fixed insulation walls; and a first insulating filler material for filling the first slits.

Abstract: The present invention relates to: an electrode assembly which can improve safety by securing the flatness and gap uniformity between pole plates; and a secondary battery using same.

Abstract: An embodiment of the present invention relates to a secondary battery, and the object of the present invention is to provide a secondary battery capable of improving the flatness of an electrode assembly and reducing internal resistance when the electrode assembly is rolled.

Abstract: An electrode assembly is prepared by stacking and winding a first electrode, a second electrode, and a separator disposed between the first and second electrodes. The electrode assembly is curved to the center of an axis that is substantially parallel to a length direction of the electrode assembly, and the separator has a coated layer of a thermoplastic polymer on at least one side thereof. A battery cell including the electrode assembly, and a method of preparing the battery cell have also been disclosed. The battery cell including the electrode assembly may have a high strength.

Abstract: A rechargeable lithium battery includes a positive electrode, a negative electrode, a separator between the positive electrode and the negative electrode, a polymer layer on the separator, the polymer layer including a polyvinylidene fluoride based polymer, and an electrolyte solution including an alkyl propionate.

Abstract: A rechargeable lithium battery includes an electrode assembly including a positive electrode including a positive current collector, a first separator on the positive electrode, a negative electrode including a negative current collector on the first separator, and a second separator on the negative electrode. The positive current collector and the negative current collector each have respective uncoated regions at two sides thereof. The first separator includes a first substrate including a polyolefin-based resin particle, and a coating layer on a side of the first substrate the coating layer being an inorganic layer or an organic layer. The second separator includes a second substrate including a polyolefin-based resin particle, and an outermost region and/or a central region of the electrode assembly includes one of the uncoated regions of the positive current collector, the first separator, one of the uncoated regions of the negative current collector and the second separator.

Abstract: A method for manufacturing a light-emitting diode device, according to the present invention, comprises: a first step of preparing a base mold (300) having a plurality of recessed accommodation parts (A); a second step of applying fluorescent resins (320) inside the accommodation parts (A); a third step of mounting, within the accommodation parts (A), light-emitting diode chips (10) having smaller widths than those of the accommodation parts (A) such that the fluorescent resins (320) are pushed up to the top over a gap between the lateral sides of the accommodation parts (A) and the light-emitting diode chips (10) so as to allow the lateral sides of the light-emitting diode chips (10) to be surrounded by the fluorescent resins (320), thereby simultaneously obtaining a plurality of individual light-emitting diode devices; and a fourth step of separating the light-emitting diode devices from the base mold (300).

Abstract: Provided is a transmitter. The transmitter includes a signal combiner configured to amplify a first differential radio frequency (RF) signal modulated to be transmitted through a first frequency band and a second differential RF signal modulated to be transmitted through a second frequency band non-adjacent to the first frequency band and summate the amplified first differential RF signal and the amplified second differential RF signal in a current mode to generate an RF signal and a power amplifier configured to amplify the generated RF signal.

Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.

Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

Abstract: Provided is a power amplifier installed in wireless communication terminals and systems. According to one aspect of the present invention, a reconfigurable power amplifier capable of selecting a wide band frequency is provided. The reconfigurable power amplifier includes input transistors receiving a radio frequency (RF) signal and a reconfigurable adaptive power cell configured to select the wide band frequency by applying a common-gate bias voltage to a plurality of common-gate transistors with a plurality of separate common gates to amplify the RF signal.

Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.

Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.

Abstract: A bandpass filter that provides a wide gain control range is provided. The bandpass filter performs channel filtering and gain control while maintaining the bandpass characteristic of the bandpass filter. The bandpass filter enables gain control for a wide signal amplitude range while maintaining performance characteristics, such as an out-of-band attenuation ratio capable of high linearity and good pass-band flatness.

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

Abstract: Disclosed is a method for manufacturing a rechargeable battery, including: stacking electrode assemblies; welding lead tabs formed in the electrode assemblies; cutting end portions of the welded lead tabs; and welding lead terminals to the cut lead tabs.