Abstract: A universal serial bus (USB) communication system includes a USB host that divides one data stream into first through (n)th sub-data streams and transmits the first through (n)th sub-data streams via first through (n)th USB host channels, respectively, a USB device that receives the first through (n)th sub-data streams via first through (n)th USB device channels, respectively and restores the data stream by combining the first through (n)th sub-data streams, and first through (n)th cables that are connected to the first through (n)th USB host channels via first through (n)th USB host ports and connected to the first through (n)th USB device channels via first through (n)th USB device ports. Here, the first through (n)th cables connect the first through (n)th USB host channels to the first through (n)th USB device channels, respectively.

Abstract: A universal serial bus (USB) communication system includes a USB host that divides one data stream into first through (n)th sub-data streams and transmits the first through (n)th sub-data streams via first through (n)th USB host channels, respectively, a USB device that receives the first through (n)th sub-data streams via first through (n)th USB device channels, respectively and restores the data stream by combining the first through (n)th sub-data streams, and first through (n)th cables that are connected to the first through (n)th USB host channels via first through (n)th USB host ports and connected to the first through (n)th USB device channels via first through (n)th USB device ports. Here, the first through (n)th cables connect the first through (n)th USB host channels to the first through (n)th USB device channels, respectively.

Abstract: A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.

Abstract: Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit.

Abstract: An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.

Abstract: A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.

Abstract: A system has a first chip using a first bus matrix, and a second chip including second and third bus matrixes connected to the first bus matrix. The second bus matrix is connected to a plurality of bus masters of the second chip and the third bus matrix is connected to a plurality of bus slaves of the second chip.

Abstract: An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.

Abstract: Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit.

Abstract: A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a variable bus occupancy rate. When an interrupt signal provided to the CPU is activated, a second rate for the CPU, which is a sum of the first rate for the CPU and the variable rate, and the first rates for the second and third master devices are applied to a bus arbiter. When the interrupt signal is inactivated, a third rate for the CPU, which is obtained by subtracting the variable rate from the first rate for the CPU, and the first rates for the second and third master devices are applied to the bus arbiter. A use priority of the system bus is controlled according to the rates applied to the bus arbiter.

Abstract: A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a variable bus occupancy rate. When an interrupt signal provided to the CPU is activated, a second rate for the CPU, which is a sum of the first rate for the CPU and the variable rate, and the first rates for the second and third master devices are applied to a bus arbiter. When the interrupt signal is inactivated, a third rate for the CPU, which is obtained by subtracting the variable rate from the first rate for the CPU, and the first rates for the second and third master devices are applied to the bus arbiter. A use priority of the system bus is controlled according to the rates applied to the bus arbiter.

Abstract: A semiconductor device for initializing an interface card using a serial EEPROM and an initializing method allow for more effective use of a serial EEPROM used to store the initialization information, while not consuming additional circuit surface area.

Abstract: A semiconductor device for initializing an interface card using a serial EEPROM and an initializing method allow for more effective use of a serial EEPROM used to store the initialization information, while not consuming additional circuit surface area..