Abstract: Method and system for calibrating exposure system for manufacturing of integrated circuits. According to an embodiment, the present invention provides a method for determining one or more focus parameters for an exposure system. As an example, the exposure system is used for forming patterns on semiconductor wafer. The method includes a step for providing a semiconductor wafer. The semiconductor wafer is characterized by a diameter. The method also includes a step for forming a plurality of patterns using the exposure system on the semiconductor wafer. As an example, each of the plurality of patterns being associated with a focus reference value (e.g., focus distance, focus angle, etc.). The method additionally includes a step for determining a plurality of shift profiles, and each of the shift profile is associated one of the plurality of patterns.

Abstract: Method and system for calibrating exposure system for manufacturing of integrated circuits. According to an embodiment, the present invention provides a method for determining one or more focus parameters for an exposure system. As an example, the exposure system is used for forming patterns on semiconductor wafer. The method includes a step for providing a semiconductor wafer. The semiconductor wafer is characterized by a diameter. The method also includes a step for forming a plurality of patterns using the exposure system on the semiconductor wafer. As an example, each of the plurality of patterns being associated with a focus reference value (e.g., focus distance, focus angle, etc.). The method additionally includes a step for determining a plurality of shift profiles, and each of the shift profile is associated one of the plurality of patterns.

Abstract: A method for photolithographic patterning in a via-first dual damascene process involving the use of a low-K dielectric material as an insulation layer on a wafer substrate during the fabrication of an integrated circuit is described. The method includes filling an aperture etched into an insulation layer on a wafer substrate with a fill-in material for isolating the insulation layer from a photoresist layer deposited thereafter and depositing a photoresist layer on the insulation layer. The method further includes exposing and developing the photoresist layer for providing a photoresist mask pattern for subsequent etching of the insulation layer; and removing the fill-in material from the aperture.