Patents by Inventor Cher Khng Victor Tan

Cher Khng Victor Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7754531
    Abstract: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: July 13, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Wuu Yean Tay, Cher Khng Victor Tan
  • Patent number: 7569473
    Abstract: Apparatus and methods are disclosed relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: August 4, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, Cher Khng Victor Tan
  • Patent number: 7368391
    Abstract: A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include one or more recessed areas that laterally surround at least a portion of the die-attach location to receive excess adhesive.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
  • Patent number: 7230330
    Abstract: Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: June 12, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, Cher Khng Victor Tan
  • Patent number: 7213447
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Chee Peng Neo, Cher Khng Victor Tan, Kian Seng Ho, Hock Chuan Tan
  • Patent number: 7112520
    Abstract: Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, Cher Khng Victor Tan
  • Patent number: 7061124
    Abstract: A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The solder may be positioned or formed on the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive excess adhesive.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: June 13, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Poh Pour
  • Patent number: 7018871
    Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: March 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
  • Publication number: 20050229684
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Application
    Filed: June 20, 2005
    Publication date: October 20, 2005
    Applicant: Micron Technology, Inc.
    Inventors: Chee Neo, Cher Khng Victor Tan, Kian Ho, Hock Tan
  • Patent number: 6923045
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 2, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Chee Peng Neo, Cher Khng Victor Tan, Kian Seng Ho, Hock Chuan Tan
  • Publication number: 20040253748
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Application
    Filed: July 15, 2004
    Publication date: December 16, 2004
    Inventors: Chee Peng Neo, Cher Khng Victor Tan, Kian Seng Ho, Hock Chuan Tan
  • Patent number: 6787923
    Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
  • Patent number: 6779386
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: August 24, 2004
    Assignee: Micron Technology Inc.
    Inventors: Chee Peng Neo, Cher Khng Victor Tan, Kian Seng Ho, Hock Chuan Tan
  • Publication number: 20040077109
    Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.
    Type: Application
    Filed: August 18, 2003
    Publication date: April 22, 2004
    Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Poh Pour
  • Publication number: 20030193092
    Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.
    Type: Application
    Filed: April 10, 2002
    Publication date: October 16, 2003
    Inventors: Cher Khng Victor Tan, Choon Kuan Lee, Kian Chai Lee, Guek Har Lim, Wuu Yean Tay, Teck Huat Poh, Cheng Pour Poh
  • Publication number: 20030164540
    Abstract: Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multi-die assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface and employed to connect stacked assemblies.
    Type: Application
    Filed: May 17, 2002
    Publication date: September 4, 2003
    Inventors: Teck Kheng Lee, Cher Khng Victor Tan
  • Publication number: 20030041656
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Chee Peng Neo, Cher Khng Victor Tan, Kian Seng Ho, Hock Chuan Tan