Abstract: A system and method for determining locations of maximum deflection of a printed circuit board (PCB) under test conditioned by boundary and loading conditions of the PCB, first vertical force magnitudes at associated first vertical force locations to be applied to the PCB by a tester fixture in a first direction, and second vertical force magnitudes at associated second vertical force locations to be applied to the PCB by the tester fixture in a second direction. Fixture components may be added to the design to the fixture design and the method iteratively executed until the magnitude of the maximum deflection is less than or equal to a predetermined maximum deflection magnitude.

Abstract: A system and method for determining locations of maximum deflection of a printed circuit board (PCB) under test conditioned by boundary and loading conditions of the PCB, first vertical force magnitudes at associated first vertical force locations to be applied to the PCB by a tester fixture in a first direction, and second vertical force magnitudes at associated second vertical force locations to be applied to the PCB by the tester fixture in a second direction. Fixture components may be added to the design to the fixture design and the method iteratively executed until the magnitude of the maximum deflection is less than or equal to a predetermined maximum deflection magnitude.

Abstract: A novel method for finding optimized solutions for assigning pins to probes in a constrained tester environment is presented. Given a test system network, including the nodes, probes, pins, resources, probe-to-resource mappings, resource-to-pin mappings, and test-to-resource mappings, and constraints including a Multiple-Resource-Per-Probe Constraint, a Same-Module Constraint, and/or a Multiplexing Constraint, the test system network is modeled as a Network Flow Problem to handle all of the constraints of the constrained pin-to-probe assignment problem, using “dummy” probes where necessary to model the constrained network. A modified Maximum Flow Algorithm that satisfies the network constraints is applied to the Network Flow Problem to generate a solution to said constrained pin-to-probe assignment problem.

Abstract: A method for determining the optimum placement of supports on a PCB of a wireless test fixture is presented. In accordance with the invention, an optimum support placement calculator determines the location of maximum deflection based on the boundary conditions and loaded conditions of the board, including the locations and forces of components loaded on the board, including traces and conductive pads, mounting hardware, electrical components, and probes contacting the board. A support is placed at the location of maximum deflection that does not coincide with any component location. The support is then added to the known boundary and loading conditions and the process repeated for additional supports until the amplitude of maximum deflection is below a predetermined maximum deflection threshold.

Abstract: A method for determining via placement for wireless test fixture printed circuit boards (PCBs) utilizes the fixed test interface pattern of the bottom conductive pads to quickly locate the nearest bottom pad to a given top pad. The distance between the top pad and its nearest bottom pad is then calculable based on the coordinates of the respective pads on the PCB. If the distance is greater than a predetermined clearance requirement, a via is placed within the interior of the nearest bottom pad; otherwise, the via is placed exterior to the nearest bottom pad.

Abstract: A novel method for finding optimized solutions for assigning pins to probes in a constrained tester environment is presented. Given a test system network, including the nodes, probes, pins, resources, probe-to-resource mappings, resource-to-pin mappings, and test-to-resource mappings, and constraints including a Multiple-Resource-Per-Probe Constraint, a Same-Module Constraint, and/or a Multiplexing Constraint, the test system network is modeled as a Network Flow Problem to handle all of the constraints of the constrained pin-to-probe assignment problem, using “dummy” probes where necessary to model the constrained network. A modified Maximum Flow Algorithm that satisfies the network constraints is applied to the Network Flow Problem to generate a solution to said constrained pin-to-probe assignment problem.

Abstract: A method for determining via placement for wireless test fixture printed circuit boards (PCBs) utilizes the fixed test interface pattern of the bottom conductive pads to quickly locate the nearest bottom pad to a given top pad. The distance between the top pad and its nearest bottom pad is then calculable based on the coordinates of the respective pads on the PCB. If the distance is greater than a predetermined clearance requirement, a via is placed within the interior of the nearest bottom pad; otherwise, the via is placed exterior to the nearest bottom pad.

Abstract: A method for determining the optimum placement of supports on a PCB of a wireless test fixture is presented. In accordance with the invention, an optimum support placement calculator determines the location of maximum deflection based on the boundary conditions and loaded conditions of the board, including the locations and forces of components loaded on the board, including traces and conductive pads, mounting hardware, electrical components, and probes contacting the board. A support is placed at the location of maximum deflection that does not coincide with any component location. The support is then added to the known boundary and loading conditions and the process repeated for additional supports until the amplitude of maximum deflection is below a predetermined maximum deflection threshold.

Abstract: A technique for minimizing the area occupied by traces on wireless fixture printed circuit boards of a printed circuit board tester on a per trace basis which ensures meeting maximum trace resistance and/or proper current delivery requirements for tests to be performed using the traces is presented. A printed circuit board implemented in accordance with the invention includes a plurality of conductive pads and a plurality of traces, each of which conductively connects at least two of said conductive pads. At least two of the traces may have differing respective cross-sectional areas predetermined to allow sufficient current to flow therethrough to drive devices connectable to said conductive pads. The cross-sectional area of each trace is calculated based on the minimum sufficient amount of current required to be delivered across the trace, the maximum allowed resistance of the trace, the trace length, and the characteristic resistance of the trace material.

Abstract: The present invention is directed to a method and apparatus for balancing forces in a fixture and reducing forces in a probe plate (208) housed in the fixture. A plurality of double-ended probes (200) are positioned in the probe plate (208). A first bit (216), located at one of the double-ended probe (200) is in contact with a board under test (206). A second bit (218), which is oppositely disposed and located on the other end of the double-ended probe (200) is in contact with a wireless PCB (202). A spring (220) runs the length of the double-ended probe (200) and is in contact with the first bit (216) and the second bit (218).

Abstract: The present invention is directed to a method and apparatus for balancing forces in a fixture and reducing forces in a probe plate housed in the fixture. A plurality of double-ended probes are positioned in the probe plate. A first bit, located at one of the double-ended probe is in contact with a board under test. A second oppositely disposed bit located on the other end of the double-ended probe is in contact with a wireless PCB. A spring runs the length of the double-ended probe and is in contact with the first bit and the second bit. As downward forces are applied from the board under test and upward forces are applied from the wireless PCB, the bits move downward and upward respectively and the spring compresses, alleviating/reducing forces in the probe plate.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.