Patents by Inventor Chern-Shyan Tsay

Chern-Shyan Tsay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for integrated circuit mask patterning
    Patent number: 9195134
    Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Min Huang, Bo-Han Chen, Lun-Wen Yeh, Shun-Shing Yang, Chia-Cheng Chang, Chern-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin
  • Method and Apparatus for Integrated Circuit Mask Patterning
    Publication number: 20150040081
    Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Min Huang, Bo-Han Chen, Lun-Wen Yeh, Shun-Shing Yang, Chia-Cheng Chang, Chern-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin