Patents by Inventor Cherng Chang Tsuei
Cherng Chang Tsuei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9613816Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.Type: GrantFiled: October 5, 2015Date of Patent: April 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsien-Chieh Tsai, Tz-Wei Lin, Sheng-Jen Yang, Hung-Yin Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
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Patent number: 9559190Abstract: A semiconductor structure includes a substrate and a metal gate. The metal gate includes a metallic filling layer and disposed over the substrate. The semiconductor structure further includes a dielectric material over the metallic filling layer and separating the metallic filling layer from a conductive trace. The conductive trace is over the dielectric material. The semiconductor structure further includes a conductive plug extending longitudinally through the dielectric material and ending with a lateral encroachment inside the metallic filling layer along a direction. The lateral direction is substantially perpendicular to the longitudinal direction of the conductive plug.Type: GrantFiled: August 25, 2015Date of Patent: January 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chien-Hung Chen, Shen-Chieh Liu, Hobin Chen, Wen-Lang Wu, Cherng-Chang Tsuei
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Patent number: 9412606Abstract: One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions.Type: GrantFiled: February 14, 2014Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9384949Abstract: A gas-flow control method for a plasma apparatus is provided. The gas-flow control method includes mounting a first adjusting mechanism on a gas-distribution plate. The gas-distribution plate includes a number of exhaust openings, and the exhaust openings in a first area of the gas-distribution plate are masked by the first adjusting mechanism. The gas-flow control method also includes exhausting a gas from the exhaust openings in a first unmasked area of the gas-distribution plate, and the gas passing through the first adjusting mechanism into a plasma chamber. The gas-flow control method further includes generating an electric field to excite the gas in the plasma chamber into plasma.Type: GrantFiled: August 8, 2014Date of Patent: July 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Zi-Neng Huang, Chang-Sheng Lee, Shen-Chieh Liu, Cherng-Chang Tsuei
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Patent number: 9362185Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.Type: GrantFiled: June 10, 2015Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9324578Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.Type: GrantFiled: January 29, 2014Date of Patent: April 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Publication number: 20160042982Abstract: A gas-flow control method for a plasma apparatus is provided. The gas-flow control method includes mounting a first adjusting mechanism on a gas-distribution plate. The gas-distribution plate includes a number of exhaust openings, and the exhaust openings in a first area of the gas-distribution plate are masked by the first adjusting mechanism. The gas-flow control method also includes exhausting a gas from the exhaust openings in a first unmasked area of the gas-distribution plate, and the gas passing through the first adjusting mechanism into a plasma chamber. The gas-flow control method further includes generating an electric field to excite the gas in the plasma chamber into plasma.Type: ApplicationFiled: August 8, 2014Publication date: February 11, 2016Inventors: Zi-Neng HUANG, Chang-Sheng LEE, Shen-Chieh LIU, Cherng-Chang TSUEI
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Publication number: 20160027649Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Hsien-Chieh TSAI, Tz-Wei LIN, Sheng-Jen YANG, Hung-Yin LIN, Cherng-Chang TSUEI, Chen-Hsiang LU
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Publication number: 20150364581Abstract: A semiconductor structure includes a substrate and a metal gate. The metal gate includes a metallic filling layer and disposed over the substrate. The semiconductor structure further includes a dielectric material over the metallic filling layer and separating the metallic filling layer from a conductive trace. The conductive trace is over the dielectric material. The semiconductor structure further includes a conductive plug extending longitudinally through the dielectric material and ending with a lateral encroachment inside the metallic filling layer along a direction. The lateral direction is substantially perpendicular to the longitudinal direction of the conductive plug.Type: ApplicationFiled: August 25, 2015Publication date: December 17, 2015Inventors: CHIEN-HUNG CHEN, SHEN-CHIEH LIU, HOBIN CHEN, WEN-LANG WU, CHERNG-CHANG TSUEI
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Patent number: 9177875Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.Type: GrantFiled: November 15, 2013Date of Patent: November 3, 2015Assignee: TAIWAN SEMINCONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsien-Chieh Tsai, Tz-Wei Lin, Sheng-Jen Yang, Hung-Yin Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
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Publication number: 20150279750Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9147767Abstract: A semiconductor structure includes a substrate and a metal gate. The metal gate includes a metallic filling layer and disposed over the substrate. The semiconductor structure further includes a dielectric material over the metallic filling layer and separating the metallic filling layer from a conductive trace. The conductive trace is over the dielectric material. The semiconductor structure further includes a conductive plug extending longitudinally through the dielectric material and ending with a lateral encroachment inside the metallic filling layer along a direction. The lateral direction is substantially perpendicular to the longitudinal direction of the conductive plug.Type: GrantFiled: February 7, 2014Date of Patent: September 29, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chien-Hung Chen, Shen-Chieh Liu, Hobin Chen, Wen-Lang Wu, Cherng-Chang Tsuei
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Publication number: 20150235877Abstract: One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Inventors: Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Publication number: 20150228793Abstract: A semiconductor structure includes a substrate and a metal gate. The metal gate includes a metallic filling layer and disposed over the substrate. The semiconductor structure further includes a dielectric material over the metallic filling layer and separating the metallic filling layer from a conductive trace. The conductive trace is over the dielectric material. The semiconductor structure further includes a conductive plug extending longitudinally through the dielectric material and ending with a lateral encroachment inside the metallic filling layer along a direction. The lateral direction is substantially perpendicular to the longitudinal direction of the conductive plug.Type: ApplicationFiled: February 7, 2014Publication date: August 13, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHIEN-HUNG CHEN, SHEN-CHIEH LIU, HOBIN CHEN, WEN-LANG WU, CHERNG-CHANG TSUEI
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Publication number: 20150214063Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.Type: ApplicationFiled: January 29, 2014Publication date: July 30, 2015Inventors: Hans-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9087793Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.Type: GrantFiled: December 11, 2013Date of Patent: July 21, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen Liao, Wei-Tai Lin, Wen-Sheng Wang, Chih-Yu Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
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Publication number: 20150179531Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9064741Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.Type: GrantFiled: December 20, 2013Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Publication number: 20150162206Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen LIAO, Wei-Tai LIN, Wen-Sheng WANG, Chih-Yu LIN, Cherng-Chang TSUEI, Chen-Hsiang LU
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Publication number: 20150140692Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsien-Chieh TSAI, Tz-Wei LIN, Sheng-Jen YANG, Hung-Yin LIN, Cherng-Chang TSUEI, Chen-Hsiang LU