Patents by Inventor Cheruvu Suryanarayana Murthy

Cheruvu Suryanarayana Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Damascene double-gate MOSFET structure and its fabrication method
    Patent number: 6686630
    Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: February 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: Hussein Ibrahim Hanafi, Erin C. Jones, Cheruvu Suryanarayana Murthy, Philip Joseph Oldiges, Leathen Shi
  • Damascene double-gate mosfet structure and its fabrication method
    Publication number: 20020105039
    Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.
    Type: Application
    Filed: February 7, 2001
    Publication date: August 8, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ARMONK, NEW YORK
    Inventors: Hussein Ibrahim Hanafi, Erin C. Jones, Cheruvu Suryanarayana Murthy, Philip Joseph Oldiges, Leathen Shi
  • Method of forming a buried bitline in a vertical DRAM device
    Publication number: 20010017384
    Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.
    Type: Application
    Filed: January 19, 2001
    Publication date: August 30, 2001
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Laertis Economikos, Hussein Ibrahim Hanafi, Thomas Safron Kanarsky, Cheruvu Suryanarayana Murthy
  • Method of forming a buried bitline in a vertical DRAM device
    Patent number: 6218236
    Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: April 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Laertis Economikos, Hussein Ibrahim Hanafi, Thomas Safron Kanarsky, Cheruvu Suryanarayana Murthy