Patents by Inventor Cheryl Pereira

Cheryl Pereira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573564
    Abstract: Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method includes providing a film stack containing a Si layer, a SiGe layer, and a Ge layer positioned between the Si layer and the SiGe layer, and selectively removing the Ge layer by etching that is selective to the Si layer and the SiGe layer, thereby forming an opening between the Si layer and the SiGe layer. According to another embodiment, the method providing a film stack containing alternating Si and Ge layers, and selectively removing the Ge layers by etching that is selective to the Si layers. According to another embodiment, the method includes providing a film stack containing a plurality of alternating SiGe and Ge layers, and selectively removing the plurality of Ge layers by etching that is selective to the SiGe layers.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Aelan Mosden, Cheryl Pereira, Subhadeep Kal
  • Publication number: 20180315665
    Abstract: Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method includes providing a film stack containing a Si layer, a SiGe layer, and a Ge layer positioned between the Si layer and the SiGe layer, and selectively removing the Ge layer by etching that is selective to the Si layer and the SiGe layer, thereby forming an opening between the Si layer and the SiGe layer. According to another embodiment, the method providing a film stack containing alternating Si and Ge layers, and selectively removing the Ge layers by etching that is selective to the Si layers. According to another embodiment, the method includes providing a film stack containing a plurality of alternating SiGe and Ge layers, and selectively removing the plurality of Ge layers by etching that is selective to the SiGe layers.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 1, 2018
    Inventors: Aelan Mosden, Cheryl Pereira, Subhadeep Kal
  • Patent number: 9991133
    Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 5, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Cheryl Pereira, Nihar Mohanty, Lior Huli
  • Publication number: 20180047584
    Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).
    Type: Application
    Filed: August 11, 2017
    Publication date: February 15, 2018
    Inventors: Cheryl Pereira, Nihar Mohanty, Lior Huli