Abstract: The sum from a floating point adder is normalized by an initial shift based on a prediction for the position of the leading one or zero in the sum. This leading-one/zero prediction is based not on the operands input to the adder, nor the result from the adder, but on the intermediate generate and propagate signals within the adder. The adder has a first stage that reduces each bit-position to a generate and a propagate signal. The adder's second stage propagates the carries in the adder using these generate and propagate signals to generate the sum. Thus the adder's first-stage logic is also used for the leading one/zero prediction, reducing cost and complexity. An ECL half-adder cell is preferably used for the adder's first stage. A zero output is added to the ECL half-adder cell at minimal cost. The shift for the leading one/zero prediction is accomplished in two stages, with a selective complement of negative sums between the two-stage shift.

Abstract: Exponents are first combined together, in a way that varies with the type of floating point operation. A single intermediate exponent result is placed on an intermediate exponent bus. This intermediate exponent is adjusted upwards for any carry-out from the operation on the mantissas, or downwards for any cancellation of leading mantissa bits, producing the final exponent result. The intermediate exponent on the intermediate exponent bus is also compared to a single criteria which is used for all types of floating point operations. Thus the compare logic may be simplified because only a single set of criteria is used for all types of operations. Alternately, the criteria may be varied depending upon the degree of precision used by all operations. Because the intermediate exponent is used, separate exponent adders are not necessary for the prediction unit and the floating point unit. Compound floating point operations may require more complex logic for combining the exponents.