Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the integer pipeline, but CISC instructions re-align the floating point pipeline. CISC instructions are sent to the floating point pipeline near the end of the integer pipeline to allow the integer pipeline to fetch memory operands for the floating point pipeline. Thus the floating point pipeline relies on the memory operand fetch facilities of the integer pipeline. Complex CISC fetch-operate instructions pass through the integer pipeline first to fetch a floating point operand, and then begin the floating point pipeline for execution of a floating point operation. However, RISC instructions only use register operands and can begin the floating point pipeline earlier, reducing latency until the floating point result is produced.

Abstract: A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC program running on the CPU by using shared floating point registers. The architecturally-defined floating point registers in the CISC instruction set are merged or folded into some of the architecturally-defined floating point registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the floating-point exception-mask and flags registers defined by each architecture are merged together so that CISC instructions and RISC instructions implicitly update the same merged flags register when executing floating point instructions.