Abstract: The present invention describes a system for enabling a host computer to reset individual client computers. The invention allows the host to apply the reset to any or all clients, and to inhibit additional resets during a host power-on event. The invention additionally allows individual client modules to reset other client modules, given that the issuer is authorized and equipped to do so.

Abstract: A computer system comprises plural single board computers that utilized shared physical storage. The computers boot from and run applications located remotely. In a preferred embodiment, a hierarchy of such computers is utilized, and the order in which they boot is set such that an optimum sequence is achieved. The computer bus serves as both a network for intercomputer communications, and a bus for intra computer communications.

Abstract: A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique.

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value.

Abstract: A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique.

Abstract: In a computer system having both peripherals having their own DMA channel arbiter and peripherals having no arbiter, a separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

Abstract: A logic circuit for allowing multiple device adapters to be connected to a single interrupt level in an interrupt level-sharing environment. The circuit provides protection of the adapters from physical damage and provides a vehicle for using certain adapters not designed for use in a level sharing environment to be used in a level sharing environment. The circuit includes means for preventing destructive current flow from one adapter to a second adapter sharing the same interrupt level. The circuit also includes means for converting the rising edge interrupt request signal to a signal useful in a level sensitive system.

Abstract: A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command.

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value.

Abstract: A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others, termed "programmable" DMA channels, are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA Channel assignment value with which the comparison was successful.

Abstract: A personal computer system which associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system there treating the edge mode signals just as if they were level mode signals.

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor.

Abstract: This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently.

Abstract: This secondary processing attachment to a primary (host) data processing system provides a dual mode I/O operation having unique "real time" applications. In this mode the attachment subsystem may exchange data concurrently with two potentially separate storage areas in host system main storage, under the direction of a single device control block (DCB) command descriptor prepared by host system software. Examples of real time processing applications include encryption and decryption of "secure" data by the attachment subsystem, matrix multiplication, or signal processing operations by the subsystem, and conservative movement of data between host storage and process control devices which link to the attachment subsystem via a device multiplexor and are co-addressed with that subsystem (by the host system).

Abstract: A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor.

Abstract: A data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value. The data storage device is disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device. The data storage device temporarily stores a predetermined amount of data while simultaneously transferring data between the processor and the I/O device. Circuitry is provided for selectively establishing a threshold storage capacity value of the data storage device wherein the threshold storage capacity value is less than the maximum storage capacity value of the data storage device.