Patents by Inventor Chester Dominic Rebeiro

Chester Dominic Rebeiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistance to cache timing attacks on block cipher encryption
    Patent number: 9813235
    Abstract: Technology is generally described for improving resistance to cache timing attacks made on block cipher encryption implementations. In some examples, the technology can include identifying one or more tunable parameters of the block cipher encryption algorithm; creating multiple encryption algorithm implementations by varying one or more of the parameter values; causing a computing system to encrypt data using the implementations; measuring average execution times at the computing system for the implementations subjecting the implementations to a cache timing attack; measuring average execution times at the computing system for the implementations subjected to a cache timing attack; computing a time difference between the average execution times for the implementations when not subjected and when subjected to a cache timing attack; selecting an implementation having a lower time difference; and using the selected implementation for a subsequent encryption operation.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: November 7, 2017
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR
    Inventors: Debdeep Mukhopadhyay, Chester Dominic Rebeiro
  • RESISTANCE TO CACHE TIMING ATTACKS ON BLOCK CIPHER ENCRYPTION
    Publication number: 20150249535
    Abstract: Technology is generally described for improving resistance to cache timing attacks made on block cipher encryption implementations. In some examples, the technology can include identifying one or more tunable parameters of the block cipher encryption algorithm; creating multiple encryption algorithm implementations by varying one or more of the parameter values; causing a computing system to encrypt data using the implementations; measuring average execution times at the computing system for the implementations subjecting the implementations to a cache timing attack; measuring average execution times at the computing system for the implementations subjected to a cache timing attack; computing a time difference between the average execution times for the implementations when not subjected and when subjected to a cache timing attack; selecting an implementation having a lower time difference; and using the selected implementation for a subsequent encryption operation.
    Type: Application
    Filed: April 25, 2013
    Publication date: September 3, 2015
    Inventors: Debdeep Mukhopadhyay, Chester Dominic Rebeiro