Abstract: A display has an array of Micro-Electro-Mechanical Switches (MEMS) display elements on a substrate such as glass. Rather than directly drive all columns of the MEMS display elements from off-substrate column drivers, column mux logic is placed on the substrate. The column mux logic uses MEMS contact-switch elements that have additional contact electrodes that touch and make electrical connection when the MEMS switch is closed, but do not touch and isolate the contact electrodes from each other when the MEMS switch is open. Smaller data words of column data is successively loaded into and stored by the MEMS column-mux, which then drives the columns of the display array. The smaller data words require fewer off-substrate connections than if all columns were driven by the off-substrate drivers. An intermediate holding voltage is applied to store column data in the column mux. Off-substrate interconnect is further reduced using on-substrate row-mux MEMS.

Abstract: Frame acceleration is achieved by driving multiple LCD frames to a flat-panel display for each CRT frame. Rather than divide the flat-panel display into an upper and a lower half, the panel is divided into many segments. These are physical segments when the panel is row-addressable so that any segment can be accessed at any time. Virtual segments are used for standard dual-scan panels. A buffer memory receives gray-scale converted pixels and arranges them into segment-blocks. Multiple LCD frames are generated and stored using data acceleration. Frame-rate-cycling (FRC) of these multiple frames is used for gray-scaling. The size of the buffer memory is significantly reduced by organizing the frames into three or more segments since input and output timing can be overlapped, allowing lines to be sent to the panel at a higher rate than received by the buffer. While physical segments are most efficient, virtual segments still reduce memory requirements, especially when the multiple LCD frames are repeated.

Abstract: The amount of time that a row of pixels in a flat-panel display is illuminated is modulated from frame-to-frame and from row-to-row. Pixels in rows that are on for a longer period of time appear brighter than pixels in rows that are on for shorter periods of time. Such line modulation is combined with frame-rate-cycling (FRC) to dramatically increase the number of gray scales that can be generated for any given number of frames in a FRC cycle, and with phase-offsetting to keep the frame period constant and to reduce flicker. An N-frame FRC cycle that previously generated N+1 gray scales now produces a full 2.sup.N gray scales. The total pixel-on time over the N frame cycle depends not just on how many frames the pixel is on, but on which frames the pixel is on. Since each row in each frame in the FRC cycle is on for a different amount of time, aliasing of the frames is greatly lessened or no longer occurs. A line modulation buffer and speeding up the pixel clock to the panel allow for greater modulation.

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated.

Abstract: A circuit system for generating phase values and frame counts, particularly adapted for liquid crystal displays is described. The phase values are generated by 8.times.8 matrices, which are formed, in turn, from smaller matrices. The circuit system handles a large number of gray scale levels, 64, which are highly linear in their shading with a reduced possibility of display flicker. Furthermore, the frame count generating circuitry are arranged with respect to the phase values generating circuitry for a highly integrated implementation for color displays.

Abstract: A circuit system for generating phase values and frame counts, particularly adapted for liquid crystal displays is described. The phase values are generated by 8.times.8 matrices, which are formed, in turn, from smaller matrices. The circuit system handles a large number of gray scale levels, 64, which are highly linear in their shading with a reduced possibility of display flicker. Furthermore, the frame count generating circuitry are arranged with respect to the phase values generating circuitry for a highly integrated implementation for color displays.

Abstract: A graphics controller drives a flat-panel display and simultaneously drives an external cathode-ray-tube (CRT) display. Horizontal clock pulses continue to be applied to the flat panel during the CRT's vertical blanking or re-trace period so that the flat panel is not left in a constant state during the entire re-trace period. Leaving the flat panel in a constant state for a long period of time can cause flicker or delayed response immediately after the re-trace period ends. Running the horizontal clocks during the re-trace period can lead to D.C. buildup or rolling flicker, believed to be caused by a polarity-inversion counter in the panel assembly which is not designed to receive additional horizontal clocks beyond the number of lines on the flat panel. D.C. buildup in the flat panel is reduced by adding a high-frequency burst of horizontal clock pulses to the flat panel during the CRT's vertical re-trace period. The burst of clock pulses adjusts the count in the polarity-inversion counter.

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated.

Abstract: The system provides for vertical or horizontal centering, or both, without the use of a memory frame buffer, of raster image data whose start time and duration cannot be controlled. The centering is accomplished by controlling the frame start time and line start time of the overall display of the raster imaging surface. This is accomplished in the case of vertical centering by detecting the time of the beginning of the first or last line, or both, of the total lines of the raster image data to be displayed an controlling the start time of a subsequent one of the frames based on that detected time. Horizontal centering is carried out by detecting the time of the beginning of the first or last column, or both, of the columns in one or more of the lines of the raster image data and controlling the start time of subsequent ones of the lines based on that detected time.

Abstract: A method and apparatus for increasing the perceived gradation of the shades in visual displays is disclosed. A plurality of signals control the intensity of a sub-pixel of a display so that display can exhibit a native number of shades. Frame rate modulation techniques are used to increase the perceived gradation. Finally, flicker is reduced by spreading the phases of the modulating pixels across time, and the horizontal and vertical axes of the display.

Abstract: An apparatus is disclosed for controlling primary color producing sub-pixels of a digitally commanded display to provide mixed colors in which sub-pixels are controlled over a programmable number N of consecutive frames to be either ON or OFF during each of the frames so that a desired time averaged brightness is produced of the primary color associated with each sub-pixel, and so that the combination of the produced time averaged brightnesss results in the color desired for the pixel to which the sub-pixels belong. The apparatus employs a modulo-N adder for programmably controlling each primary color sub-pixel by using a frame rate duty cycle approach.

Abstract: The perception of grayscale shading on a digitally commanded display is produced by commanding pixels of the display with brightness-setting signals of differing average duty cycles. Brightness-setting signals having one brightness level associated with them are phase shifted in relation to time and distributed to spaced apart pixel locations at which the one brightness level is to be produced. The energization of spatially adjacent pixels is scattered in time and pixels which are energized at the same time are selected to be spatially scattered so as to avoid the perception of visual disturbances such as flickering and surface streaming.

Abstract: The system provides for vertical or horizontal centering, or both, without the use of a memory frame buffer, of raster image data whose start time and duration cannot be controlled. The centering is accomplished by controlling the frame start time and line start time of the overall display of the raster imaging surface. This is accomplished in the case of vertical centering by detecting the time of the beginning of the first or last line, or both, of the total lines of the raster image data to be displayed and controlling the start time of a subsequent one of the frames based on that detected time. Horizontal centering is carried out by detecting the time of the beginning of the first or last column, or both, of the columns in one or more of the lines of the raster image data and controlling the start time of subsequent ones of the lines based on that detected time.

Abstract: The perception of grayscale shading on a digitally commanded display is produced by commanding pixels of the display with brightness-setting signals of differing average duty cycles. Brightness-setting signals having one brightness level associated with them are phase shifted in relation to time and distributed to spaced apart pixel locations at which the one brightness level is to be produced. The energization of spatially adjacent pixels is scattered in time and pixels which are energized at the same time are selected to be spatially scattered so as to avoid the perception of visual disturbances such as flickering and surface streaming.

Abstract: A frame rate duty cycle technique and dithering technique is applied to the output of a color look-up RAM in order to drive various flat panel displays. An integrated circuit chip in accordance with the invention includes a modulo-N gray scaling unit, where the value N is variable as well as a pixels dithering unit and a color mixing unit. A brightness spreading memory is included for mapping CRT drive values into LCD drive values.