Patents by Inventor Chester T. Ladewski

Chester T. Ladewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Validity checking arrangement for extended memory mapping of external devices
    Patent number: 4531215
    Abstract: In a telecommunications switching system, a CPU utilizes memory mapped access to a number of duplex external devices and other memories. A validity checking arrangement provides for detecting invalid external device unit numbers for memory mapped accesses by the CPU. In addition, this validity checking arrangement will determine that the CPU's operating software has attempted a memory mapped access with an invalid unit number or that a true hardware fault exists.
    Type: Grant
    Filed: June 22, 1983
    Date of Patent: July 23, 1985
    Assignee: GTE Automatic Electric Incorporated
    Inventors: Chester T. Ladewski, Harry A. Chapman, Jeffrey J. Johnston