Abstract: A method and apparatus for determining when an Input/Output (I/O) module should prefetch cache lines of data from main memory. Following a request for data from a peripheral, connected to an I/O bus which supports a flexible protocol allowing peripherals with various capabilities to operate, the I/O module will request a cache line of data from main memory containing a beginning portion of the requested data. The I/O module may then prefetch consecutive cache lines containing requested data according to the operating parameters of the peripheral requesting the data and the requested data. The I/O module may prefetch in such way that neither system bus bandwidth nor I/O bus bandwidth is wasted.

Abstract: An electronic testing system can test an electronic device which has more signal pins or pads (i.e., contacts) than the maximum number of tester probes. The testing system connects the contacts to the tester such that groups of contacts share individual tester signal lines. The testing system uses special selector logic on the device to be tested to determine which particular contacts of the groups are "currently output active", or capable of transmitting data. At each step in the testing procedure, the system can vary the sets of contacts which are chosen to be currently output active, thereby resulting in a high percentage of the possible states of the device being tested.

Abstract: An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus.