Patents by Inventor Chet J. Slabinski

Chet J. Slabinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4652873
    Abstract: A priority system for controlling the sequence in which requests made by modules, connected in parallel to a common bus, for access to the common bus is granted. A bus busy line is maintained at a first predetermined voltage if the common bus is not busy, and at a second predetermined voltage if the common bus is busy. A control and timing logic unit in each module senses the voltage on the bus busy line and permits access by the module to the common bus if the bus is at the first predetermined voltage (not busy). The control and timing logic unit then drives the voltage on the bus busy line to the second predetermined voltage, to indicate that the common bus is in use, thereby prohibiting access by other modules.
    Type: Grant
    Filed: January 18, 1984
    Date of Patent: March 24, 1987
    Assignee: The Babcock & Wilcox Company
    Inventors: Phillip C. Dolsen, Chet J. Slabinski
  • Patent number: 4503549
    Abstract: A function generator for extracting the square root or other function of a pulse width modulated input signal is disclosed. The function generator utilizes a ROM table (12) which contains values of the inverse of the desired function. Two eight-bit counters (26, 28) are clocked in proportion to the duty cycle of the input signal and the duty cycle of a flip-flop (22), which is related to the output of the ROM (12). The counters (26, 28) keep a running average of the comparison of the foregoing duty cycles and, in turn, cause a four-bit up/down counter (30) and the ROM (12) to cycle in time between the value in the ROM (12) above and below the exact input value. In this manner, the output of a four-bit up/down counter (30) is an accurate interpolated representation of the square root of the input signal.
    Type: Grant
    Filed: July 16, 1982
    Date of Patent: March 5, 1985
    Assignee: The Babcock & Wilcox Company
    Inventor: Chet J. Slabinski
  • Patent number: 4303896
    Abstract: An equalizer circuit arrangement is provided for use without readjustment for a wide range of transmission line lengths. The circuit (10) is comprised of a resistor (20) and a capacitor (22) which introduce an additional time constant delay into the transmission system in order to reduce the percentage change of the transmission line response time for the shortest line used as compared to the longest line employed. This reduction permits one equalizer to be designed and used for the complete range of transmission line lengths involved.
    Type: Grant
    Filed: May 21, 1980
    Date of Patent: December 1, 1981
    Assignee: The Babcock & Wilcox Company
    Inventor: Chet J. Slabinski