Abstract: A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

Abstract: Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

Abstract: Apparatus and method for distributed management of data objects in a network of compute nodes are disclosed herein. A first compute node interface may be communicatively coupled to a first compute node to receive a request from the first compute node for at least a portion of a particular version of a data object, wherein the first compute node interface is to include mapping information and logic, wherein the logic is to redirect the request to a second compute node interface associated with a second compute node when the second compute node is mapped to a plurality of data object addresses that includes an address associated with the data object in accordance with the mapping information, and wherein the first compute node is to receive, as a response to the request, the at least a portion of the particular version of the data object from a third compute node interface associated with a third compute node.

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

Abstract: In one embodiment, a method is provided that may include generating, at least in part by first circuitry comprised in an integrated circuit, check data based at least in part upon other data, and/or determining at least in part by the first circuitry, one or more locations of the check data and/or the other data in storage. The first circuitry may be capable of regenerating the other data based at least in part upon the check data. The method also may include issuing a request from second circuitry also comprised in the integrated circuit requesting that a wireless communication device transmit the other data, and/or receiving, by the second circuitry, a request issued from the wireless device, to retrieve the other data. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A method according to one embodiment may include communicating, by an integrated circuit, with at least one target ATA/ATAPI storage device. The method of this embodiment may also include creating, by the integrated circuit, a persistent reservation between at least one target ATA/ATAPI storage device and the integrated circuit. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A method according to one embodiment may include communicating, by an expander device, with at least one initiator engine using at least a first communication protocol and at least one target storage device using at least a second communication protocol. The method of this embodiment may also include translating, by the expander device, between first commands transmitted using the first communication protocol and second commands transmitted using the second communication protocol. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: In one embodiment, a method is provided that may include generating, at least in part, an identifier to be associated with a group of devices. The group of devices may comprise at least two devices. The identifier may be generated, at least in part, based, at least in part, upon respective source identifiers identifying, at least in part, respective sources of the at least two devices. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: A method according to one embodiment may include creating at least one of a persistent reservation and a persistent affiliation between one or more target SATA storage devices and one or more initiator engines. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: Provided are a method, system, and program for managing requests to an Input/Output (I/O) device. The I/O requests directed to the I/O device are queued and a determination is made as to whether a number of queued I/O requests exceeds a threshold. If the number of queued I/O requests exceeds the threshold, then a coalesce limit is calculated. A number of queued I/O requests not exceeding the calculated coalesce limit are coalesced into a coalesced /O request and the coalesced I/O request is transmitted.

Abstract: The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, the PMOS gates turn on and pass bit values. At the same time the adjacent NMOS gates, which are driven by the same low clock signal, shut off and prevent the passed bit values from traveling any further. The bit values are thus held between adjacent PMOS and NMOS gates. When the clock signal next goes high, the NMOS gates turn on and pass the held bit values while the PMOS gates driven by the same high clock shut off. The gates are connected by circuitry which essentially holds the bit values passed through the first associated gate until they are passed through the second associated gate. The shift register may also include gated or non-gated refresh circuitry, which operates to maintain a passed bit value.