Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.

Abstract: Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.

Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.

Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.

Abstract: Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

Abstract: Examples herein relate to a solid state drive that includes a media, a processing system, and a media command arbiter configured to permit execution of a specific allocation of storage and compute commands based on a configuration, wherein the media command arbiter is to transfer commands to the media based on the configuration. The media can be locally connected to a compute engine processing system that is configurable to perform computations on data stored in the media. The configuration can indicate a number of compute commands and storage commands that are permitted to be performed over a period of time or media bandwidth allocated to compute commands and storage commands. The processing system can include an inference engine that performs one or more of: data pattern recognition, image recognition, augmented reality overlay applications, face recognition, object recognition, or voice recognition, language translation.

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the multi-bit wide logical column in the logical row stored in a different physical row and physical one-bit wide column in one of plurality of dies.

Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.