Patents by Inventor Chetan Mehta
Chetan Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916796Abstract: End-to-end data packet flow control is described for an overlay environment of a wide area network. A method includes detecting an active session of a specific application with a source node and a destination node within an overlay environment, detecting a traffic flow from the source node to the destination node associated with the active session, mapping the traffic flow to a dedicated service processing thread of a network services appliance, mapping an identifier to the dedicated service processing thread, and forwarding the traffic flow to the destination node through the dedicated service processing thread by applying the identifier to the traffic flow.Type: GrantFiled: December 23, 2021Date of Patent: February 27, 2024Assignee: Versa Networks, Inc.Inventors: Jayakrishnan Iyer, Chetan Bali, Vignesh Chinnakkannu, Ananda Sathyanarayana, Apurva Mehta
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Patent number: 11789977Abstract: In various embodiments described in the present disclosure overrides to forecast data are disaggregated to a lowest hierarchy level and derived forecasts are created based at least in part on the results. In one example, values included in the forecast are organized into a set of dimensions where the dimensions are associated with a hierarchy level of a plurality of hierarchy levels.Type: GrantFiled: September 27, 2021Date of Patent: October 17, 2023Assignee: Amazon Technologies, Inc.Inventors: Chetan Mehta, Anish Borkar, Parnika Singh, Divya Hariharan, Anup Bharadwaj, Yasaswi Vempati
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Publication number: 20230279090Abstract: A conjugate may comprise a first component capable of binding to a therapeutic target in the eye, one or more second component(s) capable of binding to hyaluronan, and one or more third component(s) comprising hyaluronan, wherein each second component is covalently bound to the first component and non-covalently bound to a third component, a composition comprising the conjugate for use as a medicament or for use in the treatment of an eye disease and a method of treating an eye disease in a subject. Additionally, a therapeutic molecule targeted to a tissue in a patient may comprises a hyaluronic acid binding moiety and a therapeutically active agent, wherein the hyaluronic acid binding moiety comprises at least two link domains of Versican.Type: ApplicationFiled: April 14, 2023Publication date: September 7, 2023Inventors: Stefan Dengl, Rami Hannoush, Simon Theodor Hansen, Peter Michael Huelsmann, Robert Franklin Kelley, Hubert Kettenberger, Shrenik Chetan Mehta, Devin Brent Tesar
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Publication number: 20230256107Abstract: A conjugate may comprise a first component capable of binding to a therapeutic target in the eye, one or more second component(s) capable of binding to hyaluronan, and one or more third component(s) comprising hyaluronan, wherein each second component is covalently bound to the first component and non-covalently bound to a third component, a composition comprising the conjugate for use as a medicament or for use in the treatment of an eye disease and a method of treating an eye disease in a subject. Additionally, a therapeutic molecule targeted to a tissue in a patient may comprises a hyaluronic acid binding moiety and a therapeutically active agent, wherein the hyaluronic acid binding moiety comprises at least two link domains of Versican.Type: ApplicationFiled: April 14, 2023Publication date: August 17, 2023Inventors: Robert Franklin Kelley, JR., Shrenik Chetan Mehta, Devin Brent Tesar, Rami Hannoush, Simon Theodor Hansen, Stefan Dengl, Hubert Kettenberger, Peter Michael Huelsmann
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Publication number: 20230048743Abstract: The present application relates to recombinant antibodies that are engineered to alter interactions between the antibodies and one or more endogenous lipases of a host cell used to produce the antibodies. In some cases, the antibodies are mutated in the heavy chain constant region, such as at CH1, CH2, and/or CH3. In other cases, the antibodies are mutated to alter their glycosylation profile.Type: ApplicationFiled: July 8, 2022Publication date: February 16, 2023Applicant: Genentech Inc.Inventors: Elizabeth Sara Hecht, Shrenik Chetan Mehta, Wendy Noel Sandoval, Sreedhara Alavattam, Nathaniel Robert Tzizik-Swanson
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Patent number: 11193953Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.Type: GrantFiled: May 10, 2019Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
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Patent number: 10832536Abstract: Apparatuses, methods, program products, and systems are presented for guided cable management. An apparatus includes a cable module that detects a first end of a cable installed at a port of a first node, a first port module that determines whether the cable that is installed at the port is an expected cable for the port based on a cable mapping table, and a first indicator module that triggers a visual indicator at the port to visually confirm that the cable is the expected cable for the port. The apparatus includes a second port module that determines a port of a second node where a second end of the cable is expected to be installed and a second indicator module that triggers a visual indicator at the port to visually indicate that the second end of the cable is expected to be installed in the port.Type: GrantFiled: December 7, 2018Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkatesh Sainath, Jinu Joy Thomas, Daniel E. Hurlimann, Thomas Sand, Fernando Pizzano, Victor Garibay, Chetan Mehta
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Publication number: 20200184784Abstract: Apparatuses, methods, program products, and systems are presented for guided cable management. An apparatus includes a cable module that detects a first end of a cable installed at a port of a first node, a first port module that determines whether the cable that is installed at the port is an expected cable for the port based on a cable mapping table, and a first indicator module that triggers a visual indicator at the port to visually confirm that the cable is the expected cable for the port. The apparatus includes a second port module that determines a port of a second node where a second end of the cable is expected to be installed and a second indicator module that triggers a visual indicator at the port to visually indicate that the second end of the cable is expected to be installed in the port.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Inventors: Venkatesh Sainath, Jinu Joy Thomas, Daniel E. Hurlimann, Thomas Sand, Fernando Pizzano, Victor Garibay, Chetan Mehta
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Publication number: 20190265273Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.Type: ApplicationFiled: May 10, 2019Publication date: August 29, 2019Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
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Publication number: 20190243797Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
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Patent number: 10371717Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.Type: GrantFiled: August 8, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
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Patent number: 10331605Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.Type: GrantFiled: August 30, 2016Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
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Patent number: 10296484Abstract: The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled at boot-time and, in response to detection of an additional adapter received after boot-time, an additional allocation of lanes to the additional adapter is dynamically controlled. The additional allocation includes allocating unallocated lanes to the additional adapter, and re-allocating at least one lane from the initial allocation in response to the unallocated lanes being insufficient.Type: GrantFiled: December 1, 2015Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
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Patent number: 10275362Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.Type: GrantFiled: April 13, 2018Date of Patent: April 30, 2019Assignee: International Business Machines CorporationInventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
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Patent number: 10102074Abstract: The embodiments relate to dynamically allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each primary and backup adapter present, and controls an initial allocation of lanes to each detected primary adapter for maximizing adapter functionality. After the initial allocation and in response to detecting a failure of at least one primary adapter, the module dynamically switches lanes from the failed adapter to at least one of the one or more remaining primary adapters and the backup adapter.Type: GrantFiled: December 1, 2015Date of Patent: October 16, 2018Assignee: International Business Machines CorporationInventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
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Publication number: 20180232317Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
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Patent number: 10025725Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.Type: GrantFiled: June 26, 2017Date of Patent: July 17, 2018Assignee: International Business Machines CorporationInventors: VIctor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
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Publication number: 20180113813Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.Type: ApplicationFiled: June 26, 2017Publication date: April 26, 2018Inventors: VIctor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Travis J. Pizel, Fernando Pizzano, Thomas R. Sand
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Publication number: 20180060266Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.Type: ApplicationFiled: August 30, 2016Publication date: March 1, 2018Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Fernando Pizzano, Thomas R. Sand
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Publication number: 20170336440Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.Type: ApplicationFiled: August 8, 2017Publication date: November 23, 2017Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou