Abstract: A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected.

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.

Abstract: A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected.

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.

Abstract: Provided is a semiconductor package which includes a substrate that includes a chip region having an active surface and an inactive surface, and a dicing region having an active surface and an inactive surface; connection terminals disposed on the active surface that belongs to the chip region; a first molding layer that covers the active surface that belongs to the chip region and exposes a portion of the connection terminals; and a second molding layer that covers the active region that belongs to the dicing region and is disposed along the dicing region and has a different surface shape from the first molding layer so as to recognize a dicing line dividing the chip regions. The semiconductor package is manufactured using an apparatus for manufacturing a semiconductor package having a mold surface that coincides to surface shapes of the first and second molding layers.

Abstract: A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

Abstract: Provided are a wafer level stacked package with a via contact in an encapsulation portion, and a manufacturing method thereof. A plurality of semiconductor chips and encapsulation portions may be vertically deposited and electrically connected through a via contact that may be vertically formed in the encapsulation portion. Thus, an effective fan-out structure may be produced, vertical deposition may be available regardless of the type of a semiconductor device, and productivity may be improved.

Abstract: Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter.

Abstract: A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

Abstract: A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

Abstract: A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.

Abstract: A semiconductor package such as a bumped chip carrier (BCC) package has projections extending from a lower surface of a resin encapsulant. Each projection has a concave depression formed thereon. By reflowing a solder layer, external terminals are formed to cover the projections. An interface between the terminals and the projections increases in area, relative to conventional structures, because of the concave depressions. Therefore, the adhesive strength between the terminals and the projections also increases, and, when the BCC package is mounted on a next-level circuit board through the terminals, solder joint is also improved in reliability.

Abstract: A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.

Abstract: A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

Abstract: A semiconductor package such as a bumped chip carrier (BCC) package has projections extending from a lower surface of a resin encapsulant. Each projection has a concave depression formed thereon. By reflowing a solder layer, external terminals are formed to cover the projections. An interface between the terminals and the projections increases in area, relative to conventional structures, because of the concave depressions. Therefore, the adhesive strength between the terminals and the projections also increases, and, when the BCC package is mounted on a next-level circuit board through the terminals, solder joint is also improved in reliability.

Abstract: A semiconductor chip package may include functional and packaging parts, which may be separated into first and second areas respectively, and designated only for a specific type of semiconductor material. The first area may be designated only for functional material, while the second area may be designated only for packaging material. The first area may include a semiconductor chip and/or passive elements, while the second area may include packaging material for example, solder and/or contact pads.