Patents by Inventor Chew Ching Lim

Chew Ching Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11521940
    Abstract: The present disclosure relates to a semiconductor package that may include a substrate, at least one die coupled to the substrate, and a stiffener coupled to the substrate, wherein the stiffener may include a stiffener frame, wherein the stiffener frame at least partially surrounds the at least one die. The stiffener may include at least one resilient member extending from the stiffener frame towards the at least one die, and the at least one resilient member may include a distal end that extends at a height above the substrate.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: December 6, 2022
    Assignee: INTEL CORPORATION
    Inventors: Eng Kwong Lee, Chew Ching Lim
  • Patent number: 11495514
    Abstract: Disclosed embodiments include multiple thermal-interface material at the interface between an integrated heat spreader and a heat sink. A primary thermal-interface material has flow qualities and a secondary thermal-interface material has containment and adhesive qualities. The integrated heat spreader has a basin form factor that contains the primary thermal-interface material.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Chew Ching Lim, Chun Howe Sim
  • Publication number: 20220068842
    Abstract: The present disclosure relates to a semiconductor package that may include a substrate, at least one die coupled to the substrate, and a stiffener coupled to the substrate, wherein the stiffener may include a stiffener frame, wherein the stiffener frame at least partially surrounds the at least one die. The stiffener may include at least one resilient member extending from the stiffener frame towards the at least one die, and the at least one resilient member may include a distal end that extends at a height above the substrate.
    Type: Application
    Filed: November 4, 2020
    Publication date: March 3, 2022
    Inventors: Eng Kwong LEE, Chew Ching LIM
  • Publication number: 20210183727
    Abstract: Disclosed embodiments include multiple thermal-interface material at the interface between an integrated heat spreader and a heat sink. A primary thermal-interface material has flow qualities and a secondary thermal-interface material has containment and adhesive qualities. The integrated heat spreader has a basin form factor that contains the primary thermal-interface material.
    Type: Application
    Filed: September 18, 2020
    Publication date: June 17, 2021
    Inventors: Chew Ching Lim, Chun Howe Sim
  • Patent number: 9633874
    Abstract: A warpage reshaping apparatus to reshape a warpage profile of a package substrate is disclosed. The warpage reshaping apparatus includes a metal boat, a plurality of planar boards and a plurality of spring-loaded clips. The metal boat includes a plurality of cavities. Package substrates are placed into each of the cavities. Each of the plurality of planar boards is disposed on a respective one of the package substrates. The spring-loaded clips have a first portion coupled to the metal boat and having a second portion biased against a respective one of the planar boards such that each planar board is biased against its respective package substrate. In addition to that, a method to operate the warpage reshaping apparatus is also disclosed and the manner in which the warpage reshaping apparatus changes the warpage profile of the package substrate is also disclosed.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: April 25, 2017
    Assignee: Altera Corporation
    Inventors: Chew Ching Lim, Ken Beng Lim
  • Patent number: 9425174
    Abstract: An integrated circuit package may include an integrated circuit die and a package substrate having a conductive pad. A conductive pillar is formed on a front surface of the integrated circuit die and directly contacts the conductive pad. Prior to contacting the conductive pad directly, the conductive pillar may be positioned adjacent to the conductive pad such that it is aligned to the conductive pad. The integrated circuit package further includes an interconnect structure that is formed in the package substrate. The interconnect structure may include conductive traces that are electrically connected to the conductive pad and the conductive pillar. An additional integrated circuit die may be mounted on the package substrate. The additional integrated circuit die may couple to the integrated circuit die through the interconnect structure.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: August 23, 2016
    Assignee: Altera Corporation
    Inventors: Tze Yang Hin, Loon Kwang Tan, Chew Ching Lim