Patents by Inventor Chew Hoe Ang
Chew Hoe Ang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7795046Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.Type: GrantFiled: May 18, 2007Date of Patent: September 14, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Srikanteswara Dakshina-Murthy, Chew Hoe Ang
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Patent number: 7562318Abstract: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUTs).Type: GrantFiled: July 18, 2006Date of Patent: July 14, 2009Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Gang Chen, Shyue Seng Tan
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Publication number: 20090023280Abstract: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.Type: ApplicationFiled: October 1, 2008Publication date: January 22, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Chew-Hoe ANG, Dong Kyun SOHN, Liang Choo HSIA
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Patent number: 7479425Abstract: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.Type: GrantFiled: January 20, 2005Date of Patent: January 20, 2009Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Chew Hoe Ang, Dong Kyun Sohn, Liang Choo Hsia
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Publication number: 20080283878Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.Type: ApplicationFiled: May 18, 2007Publication date: November 20, 2008Inventors: Srikanteswara Dakshina-Murthy, Chew Hoe Ang
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Publication number: 20080087958Abstract: A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: ApplicationFiled: December 6, 2007Publication date: April 17, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Purakh Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Patent number: 7326609Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: GrantFiled: May 6, 2005Date of Patent: February 5, 2008Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Purakh Raj Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Publication number: 20070090484Abstract: An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.Type: ApplicationFiled: August 25, 2005Publication date: April 26, 2007Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Jae Gon Lee, Cher Sian Chua, Chew Hoe Ang, Liang-Choo Hsia
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Patent number: 7202140Abstract: A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs.Type: GrantFiled: December 7, 2005Date of Patent: April 10, 2007Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Chew Hoe Ang, Dong Kyun Sohn, Liang Choo Hsia
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Patent number: 7176094Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.Type: GrantFiled: March 6, 2002Date of Patent: February 13, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Dong Zhong, Yun Ling Tan, Chew Hoe Ang, Jia Zhen Zheng
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Publication number: 20060282804Abstract: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUTs).Type: ApplicationFiled: July 18, 2006Publication date: December 14, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chew Hoe Ang, Gang Chen, Shyue Seng Tan
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Publication number: 20060252188Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: ApplicationFiled: May 6, 2005Publication date: November 9, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Purakh Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Patent number: 7132878Abstract: This invention provides a circuit and a method for generating a low-level current using semiconductor charge pumping. The invention provides a means of generating a range of current sources by varying the frequency of a repetitive voltage pulse input signal. Also, this invention utilizes one or many MOSFET devices in order to produce higher levels of current. The current source embodiments of this invention generate very stable current sources with high input impedances.Type: GrantFiled: November 18, 2004Date of Patent: November 7, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Tupei Chen, Chew-Hoe Ang, Shyue-Seng Tan, Jia-Zhen Zheng
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Patent number: 7103861Abstract: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUT's).Type: GrantFiled: June 10, 2004Date of Patent: September 5, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Gang Chen, Shyue Seng Tan
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Patent number: 7095073Abstract: An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.Type: GrantFiled: October 25, 2004Date of Patent: August 22, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Subramanian Balakumar, Chew Hoe Ang, Jia Zhen Zheng, Paul Proctor
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Publication number: 20060160303Abstract: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.Type: ApplicationFiled: January 20, 2005Publication date: July 20, 2006Inventors: Chew-Hoe Ang, Dong Sohn, Liang Hsia
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Publication number: 20060103450Abstract: This invention provides a circuit and a method for generating a low-level current using semiconductor charge pumping. The invention provides a means of generating a range of current sources by varying the frequency of a repetitive voltage pulse input signal. Also, this invention utilizes one or many MOSFET devices in order to produce higher levels of current. The current source embodiments of this invention generate very stable current sources with high input impedances.Type: ApplicationFiled: November 18, 2004Publication date: May 18, 2006Inventors: Tupei Chen, Chew-Hoe Ang, Shyue-Seng Tan, Jia-Zhen Zheng
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Patent number: 7022625Abstract: A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first deposited on a semiconductor substrate, allowing a subsequent thermal oxidation procedure to grow a thin silicon dioxide layer on the semiconductor substrate, underlying the porous, silicon rich silicon nitride layer. A two step anneal procedure is then employed with a first step performed in a nitrogen containing ambient to densify the porous, silicon rich silicon nitride layer, while a second step of the anneal procedure, performed in an inert ambient at a high temperature, reduces the foxed charge at the silicon dioxide-semiconductor interface.Type: GrantFiled: July 25, 2002Date of Patent: April 4, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Alan Lek, Wenhe Lin
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Publication number: 20050089777Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer.Type: ApplicationFiled: November 12, 2004Publication date: April 28, 2005Inventors: Chew-Hoe Ang, Eng Lim, Randall Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
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Patent number: 6841441Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.Type: GrantFiled: January 8, 2003Date of Patent: January 11, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Eng-Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen