Patents by Inventor Chew Weng Leong

Chew Weng Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating thin integrated circuit units
    Patent number: 6468831
    Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: October 22, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Chew Weng Leong, Chee Kiang Yew, Min Yu Chan, Pang Hup Ong, Jeffrey Tuck Fook Toh, Boon Pew Chan
  • Thin integrated circuit unit
    Publication number: 20020000648
    Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.
    Type: Application
    Filed: March 16, 2001
    Publication date: January 3, 2002
    Inventors: Chew Weng Leong, Chee Kiang Yew, Min Yu Chan, Pang Hup Ong, Jeffrey Tuck Fook Toh, Boon Pew Chan
  • Stacked double sided integrated circuit package
    Patent number: 6274929
    Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: August 14, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Chew Weng Leong, Chee Kiang Yew, Min Yu Chan, Pang Hup Ong, Jeffrey Tuck Fook Toh, Boon Pew Chan
  • Thin chip-size integrated circuit package
    Patent number: 6091140
    Abstract: In accordance with the present invention, there is provided an electrically insulating substrate having first and second surfaces, an outline and an opening. A plurality of electrically conductive routing strips is integral with the substrate. A plurality of contact pads is disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A semiconductor chip is adhered to the second surface of the substrate. The chip has an outline that is substantially the same as the outline of the substrate. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to a routing strip.At least one bus bar is integral with the substrate. The bus bar is positioned remote from the substrate opening and is electrically connected to a bonding pad of the chip and to a contact pad disposed on the first surface of the substrate.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: July 18, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Tuck Fook Toh, Chew Weng Leong, Chee Kiang Yew, Pang Hup Ong